Survey of Test Vector Compression Techniques

Authors:
Nur A. Touba
Affiliations:
University of Texas at Austin
Venue:
IEEE Design & Test
Year:
2006

Citing 28
Cited 44

Using a single input to support multiple scan chains

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Test vector decompression via cyclical scan chains and its application to testing core-based designs

ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test vector encoding using partial LFSR reseeding

Proceedings of the IEEE International Test Conference 2001
Efficient compression and application of deterministic patterns in a logic BIST architecture

Proceedings of the 40th annual Design Automation Conference
Reducing Test Application Time for Full Scan Embedded Cores

FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
Efficient Seed Utilization for Reseeding based Compression

VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
A Reconfigurable Shared Scan-in Architecture

VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Reducing Test Dat Volume Using LFSR Reseeding with Seed Compression

ITC '02 Proceedings of the 2002 IEEE International Test Conference
A SmartBIST Variant with Guaranteed Encoding

ATS '01 Proceedings of the 10th Asian Test Symposium
Reducing Test Application Time Through Test Data Mutation Encoding

Proceedings of the conference on Design, automation and test in Europe
On Test Data Volume Reduction for Multiple Scan Chain Designs

VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Reconfiguration Technique for Reducing Test Time and Test Data Volume in Illinois Scan Architecture Based Designs

VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Test Data Compression and Test Resource Partitioning for System-on-a-Chip Using Frequency-Directed Run-Length (FDR) Codes

IEEE Transactions on Computers
Test data compression using dictionaries with selective entries and fixed-length indices

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Concurrent Application of Compaction and Compression for Test Time and Data Volume Reduction in Scan Designs

IEEE Transactions on Computers
Changing the Scan Enable during Shift

VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Combining dictionary coding and LFSR reseeding for test data compression

Proceedings of the 41st annual Design Automation Conference
Adjustable Width Linear Combinational Scan Vector Decompression

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Multiple Scan Tree Design with Test Vector Modification

ATS '04 Proceedings of the 13th Asian Test Symposium
XPAND: An Efficient Test Stimulus Compression Technique

IEEE Transactions on Computers
VirtualScan: A New Compressed Scan Technology for Test Cost Reduction

ITC '04 Proceedings of the International Test Conference on International Test Conference
DATA COMPRESSION FOR MULTIPLE SCAN CHAINS USING DICTIONARIES WITH CORRECTIONS

ITC '04 Proceedings of the International Test Conference on International Test Conference
Combining Linear and Non-Linear Test Vector Compression Using Correlation-Based Rectangular Encoding

VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
Variable-length input Huffman coding for system-on-a-chip test

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient test vector compression scheme using selective Huffman coding

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Embedded deterministic test

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Ring generators - new devices for embedded test applications

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Test data compression scheme based on variable-to-fixed-plus-variable-length coding

Journal of Systems Architecture: the EUROMICRO Journal
GECOM: test data compression combined with all unknown response masking

Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Using reiterative LFSR based X-masking to increase output compression in presence of unknowns

Proceedings of the 18th ACM Great Lakes symposium on VLSI
Low power Illinois scan architecture for simultaneous power and test data volume reduction

Proceedings of the conference on Design, automation and test in Europe
CASP: concurrent autonomous chip self-test using stored test patterns

Proceedings of the conference on Design, automation and test in Europe
Improving the Effectiveness of Combinational Decompressors Through Judicious Partitioning of Scan Cells

Journal of Electronic Testing: Theory and Applications
On capture power-aware test data compression for scan-based testing

Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Test Compression for IP Core Testing with Reconfigurable Network and Fixing-Flipping Coding

Journal of Electronic Testing: Theory and Applications
A Multi-Code Compression Scheme for Test Time Reduction of System-on-Chip Designs

IEICE - Transactions on Information and Systems
DX-compactor: distributed X-compaction for SoCs

Proceedings of the 19th ACM Great Lakes symposium on VLSI
System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability
A logic built-in self-test architecture that reuses manufacturing compressed scan test patterns

Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Scan power reduction in linear test data compression scheme

Proceedings of the 2009 International Conference on Computer-Aided Design
Low-power scan operation in test compression environment

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power supply noise reduction for at-speed scan testing in linear-decompression environment

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Scan cell positioning for boosting the compression of fan-out networks

Journal of Computer Science and Technology - Special section on trust and reputation management in future computing systmes and applications
Test Data Compression Using Multi-dimensional Pattern Run-length Codes

Journal of Electronic Testing: Theory and Applications
A scheme of test data compression based on coding of even bits marking and selective output inversion

Computers and Electrical Engineering
Run-length-based test data compression techniques: how far from entropy and power bounds?—a survey

VLSI Design
Reducing the storage requirements of a test sequence by using a background vector

Proceedings of the Conference on Design, Automation and Test in Europe
Test exploration and validation using transaction level models

Proceedings of the Conference on Design, Automation and Test in Europe
Scalable adaptive scan (SAS)

Proceedings of the Conference on Design, Automation and Test in Europe
LFSR-based test-data compression with self-stoppable seeds

Proceedings of the Conference on Design, Automation and Test in Europe
A generic framework for scan capture power reduction in fixed-length symbol-based test compression environment

Proceedings of the Conference on Design, Automation and Test in Europe
Modified Selective Huffman Coding for Optimization of Test Data Compression, Test Application Time and Area Overhead

Journal of Electronic Testing: Theory and Applications
Compression-aware capture power reduction for at-speed testing

Proceedings of the 16th Asia and South Pacific Design Automation Conference
Fault diagnosis aware ATE assisted test response compaction

Proceedings of the 16th Asia and South Pacific Design Automation Conference
Masking of X-Values by Use of a Hierarchically Configurable Register

Journal of Electronic Testing: Theory and Applications
Capture-power-aware test data compression using selective encoding

Integration, the VLSI Journal
SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures

Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Test Data Compression Using Selective Sparse Storage

Journal of Electronic Testing: Theory and Applications
A new scheme of test data compression based on equal-run-length coding (ERLC)

Integration, the VLSI Journal
Test-data volume and scan-power reduction with low ATE interface for multi-core SoCs

Proceedings of the International Conference on Computer-Aided Design
Tester Memory Requirements and Test Application Time Reduction for Delay Faults with Digital Captureless Test Sensors

Journal of Electronic Testing: Theory and Applications
Weighted transition based reordering, columnwise bit filling, and difference vector: a power-aware test data compression method

VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
An Efficient Block Entropy Based Compression Scheme for Systems-on-a-Chip Test Data

Journal of Signal Processing Systems
A modified scheme for simultaneous reduction of test data volume and testing power

VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Test data compression for noc based socs using binary arithmetic operations

VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Virtual scan chains reordering using a RAM-based module for high test compression

Microelectronics Journal
Reconfigurable Concurrent Error Detection Adaptive to Dynamicity of Power Constraints

Journal of Electronic Testing: Theory and Applications
An ATE assisted DFD technique for volume diagnosis of scan chains

Proceedings of the 50th Annual Design Automation Conference
Scan power reduction for linear test compression schemes through seed selection

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automating data analysis and acquisition setup in a silicon debug environment

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient Test Compression Technique for SoC Based on Block Merging and Eight Coding

Journal of Electronic Testing: Theory and Applications

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Abstract

Test data compression consists of test vector compression on the input side and response compaction on the output side. Test vector compression has been an active area of research, yielding a wide variety of techniques. This article summarizes and categorizes these techniques, explaining how they relate to one another. The goal is to provide a framework for understanding the theory and research in this area.