Two-dimensional test data compression for scan-based deterministic BIST
Proceedings of the IEEE International Test Conference 2001
Test Transformation to Improve Compaction by Statistical Encoding
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Scan Vector Compression/Decompression Using Statistical Coding
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Test Data Compression Using Dictionaries with Fixed-Length Indices
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
A MIXED MODE BIST SCHEME BASED ON RESEEDING OF FOLDING COUNTERS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Economics for Multi-site Test with Modern Cost Reduction Techniques
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
IEEE Transactions on Computers
3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Adjustable Width Linear Combinational Scan Vector Decompression
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Synchronization overhead in SOC compressed test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Survey of Test Vector Compression Techniques
IEEE Design & Test
Test data compression scheme based on variable-to-fixed-plus-variable-length coding
Journal of Systems Architecture: the EUROMICRO Journal
Test compression saves bits, cycles, and money
IEEE Design & Test
Guest Editors' Introduction: Progress in Test Compression
IEEE Design & Test
Historical Perspective on Scan Compression
IEEE Design & Test
Hierarchical Test Compression for SoC Designs
IEEE Design & Test
Multilevel-Huffman test-data compression for IP cores with multiple scan chains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-a-chip test-data compression and decompression architectures based on Golomb codes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test data compression and decompression based on internal scan chains and Golomb coding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Variable-length input Huffman coding for system-on-a-chip test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multilevel Huffman Coding: An Efficient Test-Data Compression Method for IP Cores
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A new scheme of test data compression based on equal-run-length coding (ERLC)
Integration, the VLSI Journal
An effective two-pattern test generator for Arithmetic BIST
Computers and Electrical Engineering
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A new scheme of test data compression/decompression, namely coding of even bits marking and selective output inversion, is presented. It first uses a special kind of codewords, odd bits of which are used to represent the length of runs and even bits of which are used to represent whether the codewords finish. The characteristic of the codewords make the structure of decompressor simple. It then introduces a structure of selective output inversion to increase the probability of 0s. This scheme can obtain a better compression ratio than some already known schemes, but it only needs a very low hardware overhead. The performance of the scheme is experimentally confirmed on the larger examples of the ISCAS89 benchmark circuits.