Two-dimensional test data compression for scan-based deterministic BIST

A Storage-Based Built-In Test Pattern Generation Method for Scan Circuits Based on Partitioning and Reduction of a Precomputed Test Set

IEEE Transactions on Computers

A highly regular multi-phase reseeding technique for scan-based BIST

Proceedings of the 13th ACM Great Lakes symposium on VLSI

Channel Width Test Data Compression under a Limited Number of Test Inputs and Outputs

VLSID '03 Proceedings of the 16th International Conference on VLSI Design

Embedded Deterministic Test for Low-Cost Manufacturing

IEEE Design & Test

A BIST Pattern Generator Design for Near-Perfect Fault Coverage

IEEE Transactions on Computers

Fault secureness need for next generation high performance microprocessor design for testability structures

Proceedings of the 1st conference on Computing frontiers

3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme

VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium

Adjustable Width Linear Combinational Scan Vector Decompression

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design

Hybrid BIST Based on Repeating Sequences and Cluster Analysis

Proceedings of the conference on Design, Automation and Test in Europe - Volume 2

Response shaper: a novel technique to enhance unknown tolerance for output response compaction

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design

Scan-BIST based on cluster analysis and the encoding of repeating sequences

ACM Transactions on Design Automation of Electronic Systems (TODAES)

State skip LFSRs: bridging the gap between test data compression and test set embedding for IP cores

Proceedings of the conference on Design, automation and test in Europe

System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability

A test set embedding approach based on twisted-ring counter with few seeds

Integration, the VLSI Journal

Integrated LFSR reseeding, test-access optimization, and test scheduling for core-based system-on-chip

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

A scheme of test data compression based on coding of even bits marking and selective output inversion

Computers and Electrical Engineering

Correlation-based rectangular encoding

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

MICRO: a new hybrid test data compression/ decompression scheme

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Weighted pseudorandom hybrid BIST

IEEE Transactions on Very Large Scale Integration (VLSI) Systems