Testing and build-in self-test - a survey
Journal of Systems Architecture: the EUROMICRO Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)
A Tutorial on Built-in Self-Test. I. Principles
IEEE Design & Test
Low hardware overhead scan based 3-weight weighted random BIST
Proceedings of the IEEE International Test Conference 2001
An analysis of power reduction techniques in scan testing
Proceedings of the IEEE International Test Conference 2001
Two-dimensional test data compression for scan-based deterministic BIST
Proceedings of the IEEE International Test Conference 2001
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Simultaneous reduction in test data volume and test time for TRC-reseeding
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Circular BIST with state skipping
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
HOPE: an efficient parallel fault simulator for synchronous sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Circular self-test path: a low-cost BIST technique for VLSI circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient Test Compression Technique for SoC Based on Block Merging and Eight Coding
Journal of Electronic Testing: Theory and Applications
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Test data storage, test application time and test power dissipation increase dramatically for single stuck-at faults while tens of million gates are integrated in a System-on-a-Chip (SoC), which makes implementing fault testing for embedded cores based SoC become a challenging task. To further reduce test data storage, test application time and test power dissipation, this paper presents a new test set embedding approach based on twisted-ring counter (TRC) with few seeds. This approach includes two improvements. The first is that an efficient seed-selection algorithm is employed to exploit the high-density unspecified bits in the deterministic test set and so the test data storage for complete coverage of single stuck-at faults is minimized. The second is that a novel test-sequence-reduction scheme based on shifting seeds is proposed to reduce test application time that in turn reduces test power dissipation. Compared with the conventional approach, experiments on ISCAS'89 benchmark circuits show that the proposed approach requires 65% less test data storage, 68% shorter test application time and 67% less test power dissipation. Moreover, its hardware overhead is very small.