Journal of Electronic Testing: Theory and Applications
Impact of Partial Reset on Fault Independent Testing and BIST
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
A test set embedding approach based on twisted-ring counter with few seeds
Integration, the VLSI Journal
| Hi-index | 0.03 |
A technique for designing self-test VLSI circuits, referred to as circular self-test path (CSTP), is introduced. The CSTP is a feedback shift register (output of the last flip-flop is supplied to the first flip-flop) with a data communication capability. It serves simultaneously for test pattern generation and test response compaction, thereby minimizing the test schedule complexity; the whole chip is tested in a single test session. A distinguishing attribute of built-in self-test (BIST) chips designed using this technique is a low silicon area overhead, slightly exceeding that of scan path designs, but substantially lower than that of built-in logic block observer (BILBO)-based circuits. Theoretical and simulation studies were performed to demonstrate that the test pattern generation efficiency of the CTSP is comparable to that of a pseudorandom generator, regardless of the functionality of the circuit under test