A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
Testability-based partial scan analysis
Journal of Electronic Testing: Theory and Applications - Special issue on partial scan methods
Integration of partial scan and built-in self-test
Journal of Electronic Testing: Theory and Applications - Special issue on partial scan methods
Exploiting hardware sharing in high-level synthesis for partial scan optimization
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
CRIS: a test cultivation program for sequential VLSI circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
On the Role of Hardware Reset in Synchronous Sequential Circuit Test Generation
IEEE Transactions on Computers
Producing Reliable Initialization and Test of Sequential Circuits with Pseudorandom Vectors
IEEE Transactions on Computers
Impact of Partial Reset on Fault Independent Testing and BIST
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Circular self-test path: a low-cost BIST technique for VLSI circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Partial reset has been shown to have significantimpact on test generation for sequential circuits in astored-pattern test application environment. In this paper, weexplore the use of partial reset in fault-independent testing andbuilt-in self-test (BIST) of non-scan sequential circuits. We selecta subset of flip-flops in the circuit to be resetable to logicone or zero during the application of the test vectors. Theresetting is performed with random frequency. The selection of theflip-flops and the reset polarity is based on fault-propagation analysis, which determines the impact of aselected flip-flop on fault propagation from the circuitsstructure. Application of partial reset as described above yields anaverage improvement of 15% in fault-coverage for sequentialcircuits resistant to random pattern testing. To further enhancetestability, we also present a methodology for selecting observable test points based on propagation of switchingactivity. Overall, high fault coverages (about 97%) are obtainedfor many of the ISCAS89 benchmark circuits. Thus, partial reset BISTprovides a low cost alternative for testing sequential circuits whenscan design is unacceptable due to area and/or delayconstraints. The routing overhead for implementing BIST is seen tobe about 6%.