Impact of Partial Reset on Fault Independent Testing and BIST

Authors:
H. Nguyen;A. Chatterjee;R. Roy
Affiliations:
-;-;-
Venue:
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Year:
1997

Citing 5
Cited 2

Built-in test for VLSI: pseudorandom techniques

Built-in test for VLSI: pseudorandom techniques
Testability-based partial scan analysis

Journal of Electronic Testing: Theory and Applications - Special issue on partial scan methods
Integration of partial scan and built-in self-test

Journal of Electronic Testing: Theory and Applications - Special issue on partial scan methods
On the Role of Hardware Reset in Synchronous Sequential Circuit Test Generation

IEEE Transactions on Computers
Circular self-test path: a low-cost BIST technique for VLSI circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Partial Reset Methodology and Experiments for Improving Random-Pattern Testability and BIST of Sequential Circuits

Journal of Electronic Testing: Theory and Applications
A Unified DFT Approach for BIST and External Test

Journal of Electronic Testing: Theory and Applications

Quantified Score

Hi-index	0.00

Visualization

Abstract

Partial reset has been shown to have significant impact on deterministic test generation for sequential circuits. In this paper we explore the use of partial reset in fault-independent testing and application to built-in self-test. We take the following approach: based on fault propagation analysis, we select a subset of the circuit flip-flops to be initialized to 0 or 1. The initialization (set/reset) is performed periodically while the test input vectors to the sequential circuit are applied. An average improvement of 15% in fault-coverage has been obtained for circuits resistant to random pattern testing.