On achieving a complete fault coverage for sequential machines using the transition fault model
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
An effective test generation system for sequential circuits
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Classification of Faults in Synchronous Sequential Circuits
IEEE Transactions on Computers
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Hybrid Fault Simulation for Synchronous Sequential Circuits
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
On the Use of Fully Specified Initial States for Testing of Synchronous Sequential Circuits
IEEE Transactions on Computers
A Unified DFT Approach for BIST and External Test
Journal of Electronic Testing: Theory and Applications
Does retiming affect redundancy in sequential circuits?
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
On Full Reset as a Design-For-Testability Technique
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Impact of Partial Reset on Fault Independent Testing and BIST
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
15.3 Partial Reset and Scan for Flip-Flops Based on States Requirement for Test Generation
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Synthesizing Finite State Machines for Minimum Length Synchronizing Sequence Using Partial Scan
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
| Hi-index | 14.98 |
The existence of hardware reset facilitates the test generation process for synchronous sequential circuits, as compared to test generation that starts from an unspecified initial state. Conventionally, therefore, when hardware reset is available, it is used to reset all state variables to predetermined values, conventionally 0, before a test sequence is applied. In this paper, we show that full hardware reset (i.e., reset that sets all state variables to 0) may sometimes result in test lengths and numbers of undetectable faults which are higher than the corresponding results when partial reset is used, i.e., when only a subset of the state variables are resettable, while the others retain their previous values (unspecified when the circuit is first operated) when reset is applied. The main advantage of partial reset over full reset is that while full reset is only useful once, at the beginning of a test sequence, partial reset can be used while the test sequence is being applied, to transfer the machine from one state to another. Experimental results are provided to support the use of partial reset, a procedure for selecting the state variables for partial reset is developed, and a test generation procedure valid under partial reset is presented.