PODEM-X: An automatic test generation system for VLSI logic structures
DAC '81 Proceedings of the 18th Design Automation Conference
EBT: A comprehensive test generation technique for highly sequential circuits
DAC '78 Proceedings of the 15th Design Automation Conference
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Parallel test generation for sequential circuits on general-purpose multiprocessors
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
The Multiple Observation Time Test Strategy
IEEE Transactions on Computers - Special issue on fault-tolerant computing
A state traversal algorithm using a state covariance matrix
DAC '93 Proceedings of the 30th international Design Automation Conference
Dynamic search-space pruning techniques in path sensitization
DAC '94 Proceedings of the 31st annual Design Automation Conference
Combining deterministic and genetic approaches for sequential circuit test generation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Distributed Test Pattern Generation for Stuck-At Faults in Sequential Circuits
Journal of Electronic Testing: Theory and Applications
Contest: a concurrent test generator for sequential circuits
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Split circuit model for test generation
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Efficient Techniques for Dynamic Test Sequence Compaction
IEEE Transactions on Computers
Techniques for improving the efficiency of sequential circuit test generation
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
ITEM: an iterative improvement test generation procedure for synchronous sequential circuits
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
SAT and ATPG: algorithms for Boolean decision problems
Logic Synthesis and Verification
Deterministic test pattern generation techniques for sequential circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Sequential Circuit Test Generation Using a Symbolic/Genetic Hybrid Approach
Journal of Electronic Testing: Theory and Applications
A Test-Pattern-Generation Algorithm for Sequential Circuits
IEEE Design & Test
Classification of Faults in Synchronous Sequential Circuits
IEEE Transactions on Computers
An Efficient Algorithm for Sequential Circuit Test Generation
IEEE Transactions on Computers
Application of Homing Sequences to Synchronous Sequential Circuit Testing
IEEE Transactions on Computers
On the Role of Hardware Reset in Synchronous Sequential Circuit Test Generation
IEEE Transactions on Computers
SAT and ATPG: Boolean engines for formal hardware verification
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Alternating Strategies for Sequential Circuit ATPG
EDTC '96 Proceedings of the 1996 European conference on Design and Test
MOSAIC: A Multiple-Strategy Oriented Sequential ATPG for Integrated Circuits
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Combining Symbolic and Genetic Techniques for Efficient Sequential Circuit Test Generation
ETW '00 Proceedings of the IEEE European Test Workshop
Synchronous Test Generation Model for Asynchronous Circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
MUST: Multiple-Stem Analysis for Identifying Sequentially Untestable Faults
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Putting the Squeeze on Test Sequences
ITC '97 Proceedings of the 1997 IEEE International Test Conference
LOCSTEP: A Logic Simulation-Based Test Generation Procedure
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
A New Approach to Test Generation and Test Compaction for Scan Circuits
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
TOV: sequential test generation by ordering of test vectors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DC_IATP- an iterative analog circuit test generation program for generating DC single pattern tests
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
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This paper describes a test generation system capable of high fault coverage in complex sequential circuits. Sequential logic is efficiently processed by a unidirectional time flow approach. This single path sensitization technique dynamically expands to multi-path sensitization in reconvergent fan-out structures. Sophisticated conflict analysis is used to reduce back-tracking. User guidance is also accepted to further improve performance.