An effective test generation system for sequential circuits
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
EBT: A comprehensive test generation technique for highly sequential circuits
DAC '78 Proceedings of the 15th Design Automation Conference
On the necessity to examine D-chains in diagnostic test generation-an example
IBM Journal of Research and Development
Experimental evaluation of testability measures for test generation (logic circuits)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Differential fault simulation - a fast method using minimal memory
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Iterative [simulation-based genetics + deterministic techniques]= complete ATPG0
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
SAT based ATPG using fast justification and propagation in the implication graph
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
MOSAIC: A Multiple-Strategy Oriented Sequential ATPG for Integrated Circuits
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Generation of search state equivalence for automatic test pattern generation
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
PROOFS: a super fast fault simulator for sequential circuits
EURO-DAC '90 Proceedings of the conference on European design automation
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
| Hi-index | 0.00 |
Over the years, the D-algorithm has been successfully used to generate tests for sequential circuits and combinational circuits. There are 5-valued and 9-valued circuit models used for the D-algorithm. The disadvantage of a model with lower value count is its inability to assign a more precise value for a test generation requirement without some undue assumptions or decisions which may cause backtracks or even may find no test for testable faults. However, the availability of more values increases the search space and makes enumeration more complicated. In this paper, we will present a new circuit model SPLIT which is a modified 9-valued circuit model. SPLIT has the precision of the 9-valued model and the simplicity of the 5-valued model, such that the D-algorithm will have better performance using the SPLIT model than using the 5-valued model or the 9-valued model.