Differential fault simulation for sequential circuits
Journal of Electronic Testing: Theory and Applications
Split circuit model for test generation
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Critical path tracing - an alternative to fault simulation
DAC '83 Proceedings of the 20th Design Automation Conference
STAFAN: An alternative to fault simulation
DAC '84 Proceedings of the 21st Design Automation Conference
LSI product quality and fault coverage
DAC '81 Proceedings of the 18th Design Automation Conference
The concurrent simulation of nearly identical digital networks
DAC '73 Proceedings of the 10th Design Automation Workshop
HyHOPE: a fast fault simulator with efficient simulation of hypertrophic faults
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Deterministic Built-in Pattern Generation for Sequential Circuits
Journal of Electronic Testing: Theory and Applications
A Test-Pattern-Generation Algorithm for Sequential Circuits
IEEE Design & Test
Power Reduction in Test-Per-Scan BIST
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
A hybrid fault simulator for synchronous sequential circuits
ITC'94 Proceedings of the 1994 international conference on Test
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This paper describes PROOFS, a super fast fault simulator for synchronous sequential logic circuits. PROOFS achieves high performance by combining all the advantages in differential fault simulation, single fault propagation, and parallel fault simulation to minimize the memory requirements, to reduce events that need to be simulated, and to simplify the complexity of the software implementation. The experimental results of PROOFS and other available fault simulators on 20 benchmark circuits showed that PROOFS is the best.