Exclusive simulation of activity in digital networks
Communications of the ACM
Fault-test analysis techniques based on logic simulation
DAC '72 Proceedings of the 9th Design Automation Workshop
Operational features of a MOS timing simulator
25 years of DAC Papers on Twenty-five years of electronic design automation
PODEM-X: An automatic test generation system for VLSI logic structures
25 years of DAC Papers on Twenty-five years of electronic design automation
A fault simulator for MOS LSI circuits
25 years of DAC Papers on Twenty-five years of electronic design automation
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A massively parallel algorithm for fault simulation on the connection machine
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Behavioral fault simulation in VHDL
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Extension of the critical path tracing algorithm
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Algorithms for fast, memory efficient switch-level fault simulation
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Sequential circuit fault simulation by fault information tracing algorithm: FIT
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Creator: General and efficient multilevel concurrent fault simulation
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
On efficient concurrent fault simulation for synchronous sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
HOPE: an efficient parallel fault simulator for synchronous sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
SEESIM—a fast synchronous sequential circuit fault simulator with single event equivalence
EURO-DAC '92 Proceedings of the conference on European design automation
The state of simulation in Russia
DAC '93 Proceedings of the 30th international Design Automation Conference
HyHOPE: a fast fault simulator with efficient simulation of hypertrophic faults
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
DAC '94 Proceedings of the 31st annual Design Automation Conference
New methods of improving parallel fault simulation in synchronous sequential circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Multiple Experiment Environments for Testing
Journal of Electronic Testing: Theory and Applications
An approach to fast hierarchical fault simulation
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A transistor-level logic-with-timing simulator for MOS circuits
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
ATS '95 Proceedings of the 4th Asian Test Symposium
A data structure for MOS circuits
DAC '83 Proceedings of the 20th Design Automation Conference
A design verification methodology based on concurrent simulation and clock suppression
DAC '83 Proceedings of the 20th Design Automation Conference
An MOS digital network model on a modified thevenin equivalent for logic simulation
DAC '84 Proceedings of the 21st Design Automation Conference
PODEM-X: An automatic test generation system for VLSI logic structures
DAC '81 Proceedings of the 18th Design Automation Conference
Functional simulation and fault diagnosis
DAC '78 Proceedings of the 15th Design Automation Conference
A module level simulation technique for systems composed of LSI's and MSI's
DAC '78 Proceedings of the 15th Design Automation Conference
A new test pattern generation system
DAC '80 Proceedings of the 17th Design Automation Conference
An accurate functional level concurrent fault simulator
DAC '80 Proceedings of the 17th Design Automation Conference
High-speed concurrent fault simulation with vectors and scalars
DAC '80 Proceedings of the 17th Design Automation Conference
Operational features of an MOS timing simulator
DAC '75 Proceedings of the 12th Design Automation Conference
Random test generation using concurrent logic simulation
DAC '75 Proceedings of the 12th Design Automation Conference
A new look at test generation and verification
DAC '77 Proceedings of the 14th Design Automation Conference
Concurrent fault simulation and functional level modeling
DAC '77 Proceedings of the 14th Design Automation Conference
An efficient method of fault simulation for digital circuits modeled from boolean gates and memories
DAC '77 Proceedings of the 14th Design Automation Conference
A fault simulator for MOS LSI circuits
DAC '82 Proceedings of the 19th Design Automation Conference
Speed and accuracy in digital network simulation based on structural modeling
DAC '82 Proceedings of the 19th Design Automation Conference
Computer-aided design of electrical circuits Simulation techniques (A Tutorial)
ACM '81 Proceedings of the ACM '81 conference
Digital logic simulation at the gate and functional level
DAC '79 Proceedings of the 16th Design Automation Conference
A New Approach to Fault Emulation
RSP '97 Proceedings of the 8th International Workshop on Rapid System Prototyping (RSP '97) Shortening the Path from Specification to Prototype
Overcoming the Serial Logic Simulation Bottleneck in Parallel Fault Simulation
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
The Dynamic Rollback Problem in Concurrent Event-Driven Fault Simulation
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
PROOFS: a super fast fault simulator for sequential circuits
EURO-DAC '90 Proceedings of the conference on European design automation
Design for Testability A Survey
IEEE Transactions on Computers
On the Acceleration of Test Generation Algorithms
IEEE Transactions on Computers
Efficient fault simulation on many-core processors
Proceedings of the 47th Design Automation Conference
A parallel algorithm for fault simulation on the connection machine
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
What is the path to fast fault simulation?
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Methodology for & results from the use of a hardware logic simulation engine for fault simulation
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
LSI logic testing: an overview
IEEE Transactions on Computers
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Injecting a single fault into a fault-free digital network creates a “bad” network which is only slightly dissimilar from the original. Injecting the same stimuli (signals) into both of these networks will produce activity sequences which are often identical, normally almost identical, and rarely substantially different from each other. This similarity between good and bad networks and their activities suggests a method of simulation which avoids the customary duplication of essentially identical good and bad simulations. This method consists of simulating good network activity, and of initiating and performing a concurrent bad network simulation only if bad network activity actually differs from good activity. The run time savings inherent in this method are substantial if hundreds or thousands of bad networks can be simulated in concurrence with a single good network. FANSSIM II is a digital logic simulator under development capable of simulating a 2500 gate network in concurrence with approximately 10,000 single-fault networks. The storage requirements for this simulation are estimated to remain under 450,000 bytes. The effective simulation rate is expected to be above a million signals/dollar, exceeding the real simulation rate of 20,000 signals/dollar for the IBM 360-50 by a factor of 50:1. Some of the techniques and features used are the following: • Fault sources are detected during good network activity and trigger the initiation of concurrent bad network activity. • Fault effects are transmitted piggyback via good signals or separately as independent bad signals. • Fault effects arriving at good gates cause the divergence of bad gates. • Bad gates disappear, or converge, as soon as their inputs and outputs are again in agreement with the associated good gate. • The passage of time is simulated precisely by using assignable rise and fall gate delays. • Feedback, reconvergent fanout, and race detection are handled without special mechanisms. • Economical event handling, desirable here due to accumulation of events of many bad networks, is achieved by using the time mapping6event scheduling technique.