Logic testing and design for testability
Logic testing and design for testability
Digital logic testing and simulation
Digital logic testing and simulation
Fault-tolerant computing: theory and techniques; vol. 1
A graph compaction approach to fault simulation
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Fault simulation in a distributed environment
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
High level hierarchical fault simulation techniques
CSC '85 Proceedings of the 1985 ACM thirteenth annual conference on Computer Science
STAFAN: An alternative to fault simulation
DAC '84 Proceedings of the 21st Design Automation Conference
The concurrent simulation of nearly identical digital networks
DAC '73 Proceedings of the 10th Design Automation Workshop
Test generation costs analysis and projections
DAC '80 Proceedings of the 17th Design Automation Conference
An automated method for designing logic circuit diagnostic programs
DAC '71 Proceedings of the 8th Design Automation Workshop
SMART And FAST: Test Generation for VLSI Scan-Design Circuits
IEEE Design & Test
A Deductive Method for Simulating Faults in Logic Circuits
IEEE Transactions on Computers
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Motivated by the recent advances in fast fault simulation techniques for large combinational circuits, a panel discussion has been organized for the 1988 International Test Conference. This paper is a collective account of the position statements offered by the panelists.