Stencils and problem partitionings: their influence on the performance of multiple processor systems
IEEE Transactions on Computers
IEEE Transactions on Computers
Computer Architecture and Parallel Processing
Computer Architecture and Parallel Processing
HAL: A block level HArdware Logic simulator
DAC '83 Proceedings of the 20th Design Automation Conference
Test generation costs analysis and projections
DAC '80 Proceedings of the 17th Design Automation Conference
The Yorktown Simulation Engine: Introduction
DAC '82 Proceedings of the 19th Design Automation Conference
On Distributed Fault Simulation
Computer
Fault emulation: a new approach to fault grading
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Overhead reduction techniques for hierarchical fault simulation
ATS '95 Proceedings of the 4th Asian Test Symposium
Distributed Diagnostic Simulation of Stuck-At Faults in Sequential Circuits
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
What is the path to fast fault simulation?
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
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Fault simulation of VLSI circuits takes considerable computing resources and there have been significant efforts to speed up the fault simulation process. This paper describes a distributed fault simulator implemented on a loosely-coupled network of general purpose computers. The techniques used result in a close to linear speedup and can be used effectively in most industrial VLSI CAD environments.