Differential fault simulation - a fast method using minimal memory
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Creator: General and efficient multilevel concurrent fault simulation
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Fault simulation in a distributed environment
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
LSI product quality and fault coverage
DAC '81 Proceedings of the 18th Design Automation Conference
A Deductive Method for Simulating Faults in Logic Circuits
IEEE Transactions on Computers
Functional Testing of Microprocessors
IEEE Transactions on Computers
Test Generation for Microprocessors
IEEE Transactions on Computers
| Hi-index | 0.00 |
Overhead reduction techniques for hierarchical fault simulation are presented which reduce simulation overhead for the concurrent method and its expanded version, the Multi-List-Traversal method. The techniques include a one-pass fault simulation strategy, characteristic vectors, and contiguous concurrent machines. The cost of each process for the conventional and new methods is formulated for comparison. The methods were implemented in C, and experiments were conducted using ISCAS benchmark circuits. The results show that the new techniques make conventional concurrent fault simulators up to 4.9 times faster and also that the performance can be improved by fault ordering.