Diversified Test Methods for Local Control Units
IEEE Transactions on Computers
Truth-Table Verification of an Iterative Logic Array
IEEE Transactions on Computers
Dynamic Testing of Control Units
IEEE Transactions on Computers
A heuristic chip-level test generation algorithm
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
ITC '98 Proceedings of the 1998 IEEE International Test Conference
ATS '95 Proceedings of the 4th Asian Test Symposium
Overhead reduction techniques for hierarchical fault simulation
ATS '95 Proceedings of the 4th Asian Test Symposium
Instruction Randomization Self Test For Processor Cores
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
REGISTER-TRANSFER LEVEL FAULT MODELING AND TEST EVALUATION TECHNIQUES FOR VLSI CIRCUITS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Novel Functional Test Generation Method for Processors using Commercial ATPG
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Proceedings of the 20th annual conference on Integrated circuits and systems design
Functional Testing of Microprocessors
IEEE Transactions on Computers
A hybrid software-based self-testing methodology for embedded processor
Proceedings of the 2008 ACM symposium on Applied computing
Specification-driven directed test generation for validation of pipelined processors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Testing diagnostics of modern microprocessors with the use of functional models
Automation and Remote Control
Processor Description Languages
Processor Description Languages
AFIPS '82 Proceedings of the June 7-10, 1982, national computer conference
Instruction-based self-testing of delay faults in pipelined processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
An evolutionary methodology for test generation for peripheral cores via dynamic FSM extraction
Evo'08 Proceedings of the 2008 conference on Applications of evolutionary computing
Generating power-hungry test programs for power-aware validation of pipelined processors
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
B-algorithm: a behavioral test generation algorithm
ITC'94 Proceedings of the 1994 international conference on Test
Analysis of experimental results on functional testing and diagnosis of complex circuits
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Microprocessor testing by instruction sequences derived from random patterns
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Hierarchical test generation using precomputed tests for modules
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
The KARL/KARATE system - automatic test pattern generation based on RT level descriptions
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Functional test generation of digital LSI/VLSI systems using machine symbolic execution technique
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Fault simulation at the architectural level
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Software-Based Testing for System Peripherals
Journal of Electronic Testing: Theory and Applications
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The goal of this paper is to develop test generation procedures for testing microprocessors in a user environment. Classical fault detection methods based on the gate and flip-flop level or on the state diagram level description of microprocessors are not suitable for test generation. The problem is further compounded by the availability of a large variety of microprocessors which differ widely in their organization, instruction repertoire, addressing modes, data storage, and manipulation facilities, etc. In this paper, a general graph-theoretic model is developed at the register transfer level. Any microprocessor can be easily modeled using information only about its instruction set and the functions performed. This information is readily available in the user's manual. A fault model is developed on a functional level quite independent of the implementation details. The effects of faults in the fault model are investigated at the level of the graph-theoretic model. Test generation procedures are proposed which take the microprocessor organization and the instruction set as parameters and generate tests to detect all the faults in the fault model. The complexity of the test sequences measured in terms of the number of instructions is given. Our effort in generating tests for a real microprocessor and evaluating their fault coverage is described.