Functional test generation of digital LSI/VLSI systems using machine symbolic execution technique

  • Authors:

  • Tonysheng Lin;Stephen Y. H. Su

  • Affiliations:

  • Thomas J. Watson School of Engineering, Applied Science and Technology, State University of New York, Binghamton, NY;Thomas J. Watson School of Engineering, Applied Science and Technology, State University of New York, Binghamton, NY

  • Venue:
  • ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
  • Year:
  • 1984

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Abstract

This paper presents a new algorithm for functional test generation of digital LSI/VLSI systems. First, a register-transfer (RT)-level fault model is developed based on a well-defined register-transfer-language (RTL). The analysis and collapsing of faults in RT-level fault model were performed. Then, the RT-level symbolic execution technique is employed. The major problems encountered are defined, analyzed and solved. Finally, an explicit algorithmic test generation algorithm is developed. This practical algorithm applies software skills in hardware testing. It is easy to be automated and hence provides a promising solution for future testing problems of digital LSI/VLSI systems.