Test Generation for Microprocessors
IEEE Transactions on Computers
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IEEE Transactions on Computers
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IEEE Transactions on Computers
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IEEE Transactions on Computers
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Journal of Systems Architecture: the EUROMICRO Journal
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System-on-Chip Test Architectures: Nanometer Design for Testability
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ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
| Hi-index | 14.98 |
This paper presents a new and systematic method to generate tests for microprocessors. A functional level model for the microprocessor is used and it is represented by a reduced graph. A new and comprehensive model of the instruction execution process is developed. Various types of faults are analyzed and it is shown that with the use of appropriate codewords all faults can be classified into three types. This gives rise to a systematic procedure to generate tests which is independent of the microprocessor implementation details. Tests are given to detect faults in any microprocessor, first for the READ register instructions, and then for the remaining instructions. These tests can be executed by the microprocessor in a self-test mode, thus dispensing with the need for an external tester.