Automatic functional test program generation for microprocessors
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Test generation for Gigahertz processors using an automatic functional constraint extractor
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Deterministic software-based self-testing of embedded processor cores
Proceedings of the conference on Design, automation and test in Europe
On the test of microprocessor IP cores
Proceedings of the conference on Design, automation and test in Europe
A Novel Functional Test Generation Method for Processors Using Commercial ATPG
Proceedings of the IEEE International Test Conference
Functional Testing of Current Microprocessors (applied to the Intel i860TM)
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Embedded Test and Debug of Full Custom and Synthesizable Microprocessor Cores
ETW '00 Proceedings of the IEEE European Test Workshop
A novel methodology for hierarchical test generation using functional constraint composition
HLDVT '00 Proceedings of the IEEE International High-Level Validation and Test Workshop (HLDVT'00)
A Novel Hierarchical Test Generation Method for Processors
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Instruction Randomization Self Test For Processor Cores
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
FRITS " A Microprocessor Functional BIST Method
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Effective Software Self-Test Methodology for Processor Cores
Proceedings of the conference on Design, automation and test in Europe
A genetic algorithm-based system for generating test programs for microprocessor IP cores
ICTAI '00 Proceedings of the 12th IEEE International Conference on Tools with Artificial Intelligence
Instruction-Based Self-Testing of Processor Cores
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Fully Automatic Test Program Generation for Microprocessor Cores
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Software-Based Self-Testing of Embedded Processors
IEEE Transactions on Computers
Functional Testing of Microprocessors
IEEE Transactions on Computers
Test Generation for Microprocessors
IEEE Transactions on Computers
Software-based self-testing with multiple-level abstractions for soft processor cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Software-based self-testing methodology for processor cores
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Effective software-based self-test strategies for on-line periodic testing of embedded processors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Adaptive online testing for efficient hard fault detection
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
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Software-based self-test (SBST) is emerging as a promising technology for enabling at-speed testing of high-speed embedded processors testing in an SoC system. For SBST, test routine development or generation can base on deterministic and random methodology. The deterministic test methodology develops the test program for a pipeline processor using the information abstracted from its architecture model, RTL descriptions, and gate-level net-list for different types of processor circuits. The random test methodology tries to make the pseudo-exhaustive testing possible using random instructions or patterns. The proposed methodology improves coverage for structural faults using both deterministic and random development of the test code. Not only can the deterministic test program test lots of faults using very small code size, but also the random test program can help detect some of the faults that the deterministic test program is difficult to test. We demonstrated the feasibility of the proposed methodology by the achieved fault coverage, test program size, and testing cycle count on a complex pipeline processor core. Comparisons with previous work are also made. Experimental results show its potential as an effective method for practical use.