Automatic test knowledge extraction from VHDL (ATKET)
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Pentium Processor System Architecture
Pentium Processor System Architecture
The Effect of Different Test Sets on Quality Level Prediction: When is 80% better than 90%?
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
ARTEST: An Architectural Level Test Generator for Data Path Faults and Control Faults
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
A Novel Functional Test Generation Method for Processors Using Commercial ATPG
Proceedings of the IEEE International Test Conference
Behavioral-Test Generation using Mixed-Integer Non-linear Programming
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Embedded hardware and software self-testing methodologies for processor cores
Proceedings of the 37th Annual Design Automation Conference
A scalable software-based self-test methodology for programmable processors
Proceedings of the 40th annual Design Automation Conference
DPDAT: DATA PATH DIRECT ACCESS TESTING
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A novel RTL behavioral description based ATPG method
Journal of Computer Science and Technology
Automatic Functional Test Generation - A Reality
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Software-based self-test methodology for crosstalk faults in processors
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
On the identification of modular test requirements for low cost hierarchical test path construction
Integration, the VLSI Journal
Software-based self-testing with multiple-level abstractions for soft processor cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A hybrid software-based self-testing methodology for embedded processor
Proceedings of the 2008 ACM symposium on Applied computing
MYGEN: automata-based on-line test generator for assertion-based verification
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Automatic constraint based test generation for behavioral HDL models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Coverage driven high-level test generation using a polynomial model of sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Guided gate-level ATPG for sequential circuits using a high-level test generation approach
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Fast enhancement of validation test sets for improving the stuck-at fault coverage of RTL circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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