Automatic test knowledge extraction from VHDL (ATKET)
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Test generation for Gigahertz processors using an automatic functional constraint extractor
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
A Novel Functional Test Generation Method for Processors Using Commercial ATPG
Proceedings of the IEEE International Test Conference
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A scalable software-based self-test methodology for programmable processors
Proceedings of the 40th annual Design Automation Conference
Instruction Randomization Self Test For Processor Cores
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
DEFUSE: A Deterministic Functional Self-Test Methodology for Processors
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Test Program Synthesis for Path Delay Faults in Microprocessor Cores
ITC '00 Proceedings of the 2000 IEEE International Test Conference
FRITS " A Microprocessor Functional BIST Method
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Generation of Low Power Dissipation and High Fault Coverage Patterns for Scan-Based BIST
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Noise-Aware Driver Modeling for Nanometer Technology
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Embedded software-based self-test for system-on-a-chip design
Embedded software-based self-test for system-on-a-chip design
Software-based self-testing methodology for processor cores
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Simulation-Based Functional Test Generation for Embedded Processors
IEEE Transactions on Computers
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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Due to signal integrity problems inherent sensitivity to timing, power supply voltage and temperature, it is desirable to test AC failures such as crosstalk-induced errors at operational speed and in the circuit's natural operational environment. To overcome the daunting cost and increasing performance hindrance of high-speed external testers, Software-Based. Self-Test (SBST) is proposed as a high-quality. low-cost at-speed testing solution for AC failures in programmable processors and System-on-Chips (SoC). SBST utilizes low-cost testers, applies tests and captures test responses in the natural operational environment. Hence SBST avoids artificial testing environment and external tester induced inaccuracies. Different from testing for stuck-at faults, testing for crosstalk faults requires a sequence of test vectors delivered at the operational speed. SBST applies tests in functional mode using instructions. Different instructions impose different controllability and observability constraints on a module-under-test (MUT). The complexity of searching for an appropriate sequence of instructions and operands becomes prohibitively high. In this paper, we propose a novel methodology to conquer the complexity challenge by efficiently combining structural test generation technique with instruction-level constraints. MUT in several time frames is automatically flattened and augmented with Super Virtual Constraint Circuits (SuperVCCs), which guide an automatic test pattern generation (ATPG) tool to select. appropriate test instructions and operands. The proposed methodology enables automatic test-program generation and high-fidelity test solution:for AC failures. Experimental results are shown on a commercial embedded processor (Xtensa/sup /spl trade// from Tensilica Inc).