On the test of microprocessor IP cores
Proceedings of the conference on Design, automation and test in Europe
Instruction-level DFT for testing processor and IP cores in system-on-a-chip
Proceedings of the 38th annual Design Automation Conference
Test of future system-on-chips
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Characteristic faults and spectral information for logic BIST
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A scalable software-based self-test methodology for programmable processors
Proceedings of the 40th annual Design Automation Conference
Designing Self Test Programs for Embedded DSP Cores
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Re-configurable embedded core test protocol
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Delay Fault Testing of Core-Based Systems-on-a-Chip
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Fully Automatic Test Program Generation for Microprocessor Cores
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
New evolutionary techniques for test-program generation for complex microprocessor cores
GECCO '05 Proceedings of the 7th annual conference on Genetic and evolutionary computation
Automatic generation of test sets for SBST of microprocessor IP cores
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Testing Embedded Sequential Cores in Parallel Using Spectrum-Based BIST
IEEE Transactions on Computers
Instruction-level test methodology for CPU core self-testing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Software-based self-test methodology for crosstalk faults in processors
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Software-based self-test of processors under power constraints
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A Self Test Program Design Technique for Embedded DSP Cores
Journal of Electronic Testing: Theory and Applications
Modular and rapid testing of SOCs with unwrapped logic blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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At-speed testing is becoming increasingly difficult with external testers as the speed of microprocessors approaches the GHz range. One solution to this problem is built-in self-test. However, due to their reliance on random patterns, current logic BIST techniques are not able to deal with large designs without adding high-test overhead.In this paper, we propose a functional self-test technique that is deterministic in nature. By targeting the structural test need of manageable components with the aid of processor functionality, this technique has the fault coverage advantage of deterministic structural testing and the at-speed advantage of functional testing. Most importantly, by relieving testers from test application, it enables at-speed testing of GHz processors with low speed testers. We have demonstrated our methodology on a simple accumulator-based microprocessor. The results show that with the proposed technique, we are able to apply high-quality at-speed tests with no test overhead.