Instruction-level DFT for testing processor and IP cores in system-on-a-chip
Proceedings of the 38th annual Design Automation Conference
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testability Analysis and ATPG on Behavioral RT-Level VHDL
Proceedings of the IEEE International Test Conference
A scalable software-based self-test methodology for programmable processors
Proceedings of the 40th annual Design Automation Conference
A STAFAN-like functional testability measure for register-level circuits
ATS '95 Proceedings of the 4th Asian Test Symposium
Instruction Randomization Self Test For Processor Cores
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
DEFUSE: A Deterministic Functional Self-Test Methodology for Processors
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Test Program Synthesis for Path Delay Faults in Microprocessor Cores
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Low-Cost Software-Based Self-Testing of RISC Processor Cores
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Fully Automatic Test Program Generation for Microprocessor Cores
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Software-based self-testing of microprocessors
Journal of Systems Architecture: the EUROMICRO Journal
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This paper describes a self test program design technique for embedded DSP cores. The method requires minimal knowledge of the core's internals and minimal insertion of external LFSR hardware, without scan insertions. The test program consists of a small set of instructions which operate iteratively on pseudorandom data generated by the LFSRs to fully test the DSP core components. The method uses instruction-based test metrics and a program template as a blueprint to generate the test program. The self test scheme has been successfully applied on an industrial-strength DSP core and the results compare favorably to other methods using ATPG and pseudorandom BIST.