Pentium Pro and Pentium II system architecture (2nd ed.)
Pentium Pro and Pentium II system architecture (2nd ed.)
Embedded software-based self-testing for SoC design
Proceedings of the 39th annual Design Automation Conference
System-on-a-Chip: Design and Test
System-on-a-Chip: Design and Test
Pseudorandom Testing of Microprocessors an Instruction/Data Flow Level
EDCC-2 Proceedings of the Second European Dependable Computing Conference on Dependable Computing
In-System Testing of Cache Memories
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Functional Testing of Current Microprocessors (applied to the Intel i860TM)
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Coverage directed test generation for functional verification using bayesian networks
Proceedings of the 40th annual Design Automation Conference
A scalable software-based self-test methodology for programmable processors
Proceedings of the 40th annual Design Automation Conference
Superscalar Processor Validation at the Microarchitecture Level
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Verification of Processor Microarchitectures
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Instruction Randomization Self Test For Processor Cores
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Experimental Evaluation of CPU Performance Features
DSD '01 Proceedings of the Euromicro Symposium on Digital Systems Design
Scan Islands - A Scan Partitioning Architecture and its Implementation on the Alpha 21364 Processor
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Instruction-Based Delay Fault Self-Testing of Processor Cores
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Designing Self Test Programs for Embedded DSP Cores
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Automatic Test Program Generation: A Case Study
IEEE Design & Test
Low-Cost Software-Based Self-Testing of RISC Processor Cores
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Fully Automatic Test Program Generation for Microprocessor Cores
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Efficient Template Generation for Instruction-Based Self-Test of Processor Cores
ATS '04 Proceedings of the 13th Asian Test Symposium
Test Instruction Set (TIS) for High Level Self-Testing of CPU Cores
ATS '04 Proceedings of the 13th Asian Test Symposium
Functional Coverage Driven Test Generation for Validation of Pipelined Processors
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Fault-tolerant design of the IBM pSeries 690 system using POWER4 processor technology
IBM Journal of Research and Development
Software-based self-testing methodology for processor cores
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Journal of Systems and Software
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Hardware-based self-testing techniques have limitations in the performance and area overhead. Those can be eliminated using software-based self-testing. In this paper, we investigate capabilities of the microprocessor testing by software procedures taking into account system environment constraints. Special attention is paid to microarchitectural features of pipelined and superscalar processors. New test strategies are proposed combining deterministic and pseudo-random approaches supported by the available hardware mechanisms (test registers, on-chip monitoring circuitry, etc.), which improve testability features. The test effectiveness is studied using various test coverage measures (stimuli, circuit stressing), statistical and fault injection tools. To demonstrate the utility of the proposed methodology, it has been applied to commercial microprocessors and experimental results are presented in this paper.