Arithmetic built-in self-test for embedded systems
Arithmetic built-in self-test for embedded systems
On the test of microprocessor IP cores
Proceedings of the conference on Design, automation and test in Europe
Embedded Software-Based Self-Test for Programmable Core-Based Designs
IEEE Design & Test
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Instruction Randomization Self Test For Processor Cores
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Effective Software Self-Test Methodology for Processor Cores
Proceedings of the conference on Design, automation and test in Europe
Instruction-Based Self-Testing of Processor Cores
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Software-based self-testing methodology for processor cores
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Designing Self Test Programs for Embedded DSP Cores
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Automatic Test Program Generation: A Case Study
IEEE Design & Test
New evolutionary techniques for test-program generation for complex microprocessor cores
GECCO '05 Proceedings of the 7th annual conference on Genetic and evolutionary computation
Software-based self-test of processors under power constraints
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A Self Test Program Design Technique for Embedded DSP Cores
Journal of Electronic Testing: Theory and Applications
Software-based self-testing of microprocessors
Journal of Systems Architecture: the EUROMICRO Journal
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Software self-testing of embedded processor cores which effectively partitions the testing effort between low-speed external equipment and internal processor resources, has been recently proposed as an alternative to classical hardware built-in self-test techniques over which it provides significant advantages. In this paper we present a low-cost software-based self-testing methodology for processor cores with the aim of producing compact test code sequences developed with a limited engineering effort and achieving a high fault coverage for the processor core. The objective of small test code sequences is directly related to the utilization of low-speed external testers since test time is primarily determined by the time required to download the test code to the processor memory at the testerýs low frequency. Successful application of the methodology to a RISC processor core architecture with a 3-stage pipeline is demonstrated.