The SPARC architecture manual: version 8
The SPARC architecture manual: version 8
High-level test generation for design verification of pipelined microprocessors
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 37th Annual Design Automation Conference
On the test of microprocessor IP cores
Proceedings of the conference on Design, automation and test in Europe
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Superscalar Processor Validation at the Microarchitecture Level
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Performance and Functional Verification of Microprocessors
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Code Generation for Functional Validation of Pipelined Microprocessors
ETW '03 Proceedings of the 8th IEEE European Test Workshop
Automatic test program generation for pipelined processors
Proceedings of the 2003 ACM symposium on Applied computing
Low-Cost Software-Based Self-Testing of RISC Processor Cores
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Fully Automatic Test Program Generation for Microprocessor Cores
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
An enhanced framework for microprocessor test-program generation
EuroGP'03 Proceedings of the 6th European conference on Genetic programming
Automatic generation of test sets for SBST of microprocessor IP cores
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
An effective technique for minimizing the cost of processor software-based diagnosis in SoCs
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Software-based self-testing of microprocessors
Journal of Systems Architecture: the EUROMICRO Journal
Efficient techniques for automatic verification-oriented test set optimization
International Journal of Parallel Programming
Evolving combinatorial problem instances that are difficult to solve
Evolutionary Computation
Towards Automating Simulation-Based Design Verification Using ILP
Inductive Logic Programming
Integrated verification approach during ADL-driven processor design
Microelectronics Journal
Design validation of multithreaded architectures using concurrent threads evolution
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Programming and Computing Software
Generating power-hungry test programs for power-aware validation of pipelined processors
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
A framework for testing hardware-software security architectures
Proceedings of the 26th Annual Computer Security Applications Conference
Feedback-based coverage directed test generation: an industrial evaluation
HVC'10 Proceedings of the 6th international conference on Hardware and software: verification and testing
A novel mutation-based validation paradigm for high-level hardware descriptions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Evolution of test programs exploiting a FSM processor model
EvoApplications'11 Proceedings of the 2011 international conference on Applications of evolutionary computation - Volume Part II
Journal of Electronic Testing: Theory and Applications
Coverage-Directed Test Generation Automated by Machine Learning -- A Review
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automatic completion and refinement of verification sets for microprocessor cores
EC'05 Proceedings of the 3rd European conference on Applications of Evolutionary Computing
Use of an evolutionary tool for antenna array synthesis
EC'05 Proceedings of the 3rd European conference on Applications of Evolutionary Computing
Software-Based Testing for System Peripherals
Journal of Electronic Testing: Theory and Applications
Manipulation of Training Sets for Improving Data Mining Coverage-Driven Verification
Journal of Electronic Testing: Theory and Applications
GABES: A genetic algorithm based environment for SEU testing in SRAM-FPGAs
Journal of Systems Architecture: the EUROMICRO Journal
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Comprehensive coverage measurement should guide an effective testbench generation approach. Today, feedback from coverage to test generation often requires manual work; it is desirable to implement a framework that automates this feedback process. The authors propose a genetic-algorithm-based evolution framework for testbench generation. It enables small test programs to evolve and effectively capture target corner cases based on the feedback from coverage measurement.