Automatic test program generation for pipelined processors
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Architecture validation for processors
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Formal requirements for virtualizable third generation architectures
Communications of the ACM
Proceedings of the 38th annual Design Automation Conference
Architectural support for copy and tamper resistant software
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
Symbolic Simulation: An ACL2 Approach
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Coverage directed test generation for functional verification using bayesian networks
Proceedings of the 40th annual Design Automation Conference
AEGIS: architecture for tamper-evident and tamper-resistant processing
ICS '03 Proceedings of the 17th annual international conference on Supercomputing
Xen and the art of virtualization
SOSP '03 Proceedings of the nineteenth ACM symposium on Operating systems principles
Efficient Memory Integrity Verification and Encryption for Secure Processors
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Automatic Test Program Generation: A Case Study
IEEE Design & Test
Improving SAT-Based Bounded Model Checking by Means of BDD-Based Approximate Traversals
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Architecture for Protecting Critical Secrets in Microprocessors
Proceedings of the 32nd annual international symposium on Computer Architecture
Architecture Support for 3D Obfuscation
IEEE Transactions on Computers
Modular verification of code with SAT
Proceedings of the 2006 international symposium on Software testing and analysis
QEMU, a fast and portable dynamic translator
ATEC '05 Proceedings of the annual conference on USENIX Annual Technical Conference
Understanding data lifetime via whole system simulation
SSYM'04 Proceedings of the 13th conference on USENIX Security Symposium - Volume 13
vTPM: virtualizing the trusted platform module
USENIX-SS'06 Proceedings of the 15th conference on USENIX Security Symposium - Volume 15
A Survey of Hybrid Techniques for Functional Verification
IEEE Design & Test
Hardware-rooted trust for secure key management and transient trust
Proceedings of the 14th ACM conference on Computer and communications security
Lares: An Architecture for Secure Active Monitoring Using Virtualization
SP '08 Proceedings of the 2008 IEEE Symposium on Security and Privacy
TEC-Tree: A Low-Cost, Parallelizable Tree for Efficient Defense Against Memory Replay Attacks
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
The Reduced Address Space (RAS) for Application Memory Authentication
ISC '08 Proceedings of the 11th international conference on Information Security
Lest we remember: cold boot attacks on encryption keys
SS'08 Proceedings of the 17th conference on Security symposium
Hypervisor support for identifying covertly executing binaries
SS'08 Proceedings of the 17th conference on Security symposium
MCMAS: A Model Checker for the Verification of Multi-Agent Systems
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
Parallelizable authentication trees
SAC'05 Proceedings of the 12th international conference on Selected Areas in Cryptography
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New security architectures are difficult to prototype and test at the design stage. Fine-grained monitoring of the interactions between hardware, the operating system and applications is required. We have designed and prototyped a testing framework, using virtualization, that can emulate the behavior of new hardware mechanisms in the virtual CPU and can perform a wide range of hardware and software attacks on the system under test. Our testing framework provides APIs for monitoring hardware and software events in the system under test, launching attacks, and observing their effects. We demonstrate its use by testing the security properties of the Secret Protection (SP) architecture using a suite of attacks. We show two important lessons learned from the testing of the SP architecture that affect the design and implementation of the architecture. Our framework enables extensive testing of hardware-software security architectures, in a realistic and flexible environment, with good performance provided by virtualization.