Introduction to HOL: a theorem proving environment for higher order logic
Introduction to HOL: a theorem proving environment for higher order logic
Linking BDD-based symbolic evaluation to interactive theorem-proving
DAC '93 Proceedings of the 30th international Design Automation Conference
Automatic test program generation for pipelined processors
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Architecture validation for processors
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
The formal verification of a pipelined double-precision IEEE floating-point multiplier
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
The automatic generation of functional test vectors for Rambus designs
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Validation coverage analysis for complex digital designs
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Formal verification of FIRE: a case study
DAC '97 Proceedings of the 34th annual Design Automation Conference
Abstraction Techniques for Validation Coverage Analysis and Test Generation
IEEE Transactions on Computers
What's between simulation and formal verification? (extended abstract)
DAC '98 Proceedings of the 35th annual Design Automation Conference
Approximate reachability with BDDs using overlapping projections
DAC '98 Proceedings of the 35th annual Design Automation Conference
Combining theorem proving and trajectory evaluation in an industrial environment
DAC '98 Proceedings of the 35th annual Design Automation Conference
Validation with guided search of the state space
DAC '98 Proceedings of the 35th annual Design Automation Conference
Enhancing simulation with BDDs and ATPG
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Probabilistic state space search
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Improving coverage analysis and test generation for large designs
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Modeling design constraints and biasing in simulation using BDDs
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Automatic lighthouse generation for directed state space search
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Ivy: a preprocessor and proof checker for first-order logic
Computer-Aided reasoning
POPL '77 Proceedings of the 4th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
A hybrid verification approach: getting deep into the design
Proceedings of the 39th annual Design Automation Conference
Deriving a simulation input generator and a coverage metric from a formal specification
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
Computer-Aided Reasoning: An Approach
Computer-Aided Reasoning: An Approach
SIVA: A System for Coverage-Directed State Space Search
Journal of Electronic Testing: Theory and Applications
Smart simulation using collaborative formal and simulation engines
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Coverage-Directed Test Generation Using Symbolic Techniques
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Counter-Example Based Predicate Discovery in Predicate Abstraction
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Combining Model Checking and Deduction for I/O-Automata
TACAS '95 Proceedings of the First International Workshop on Tools and Algorithms for Construction and Analysis of Systems
A Hybrid Approach to Verifying Liveness in a Symmetric Multi-Processor
TPHOLs '97 Proceedings of the 10th International Conference on Theorem Proving in Higher Order Logics
Adding External Decision Procedures to HOL90 Securely
Proceedings of the 11th International Conference on Theorem Proving in Higher Order Logics
Construction of Abstract State Graphs with PVS
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Syntactic Program Transformations for Automatic Abstraction
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
On Combining Formal and Informal Verification
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
An LCF-Style Interface between HOL and First-Order Logic
CADE-18 Proceedings of the 18th International Conference on Automated Deduction
PVS: A Prototype Verification System
CADE-11 Proceedings of the 11th International Conference on Automated Deduction: Automated Deduction
Coverage directed test generation for functional verification using bayesian networks
Proceedings of the 40th annual Design Automation Conference
Practical Use of Sequential ATPG for Model Checking: Going the Extra Mile Does Pay Off
HLDVT '01 Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop (HLDVT'01)
Automatic Validation Test Generation Using Extracted Control Models
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Verifying Properties Using Sequential ATPG
ITC '02 Proceedings of the 2002 IEEE International Test Conference
A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based Coverage
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Program Slicing for ATPG-Based Property Checking
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Linking Simulation with Formal Verification at a Higher Level
IEEE Design & Test
Functional Coverage Driven Test Generation for Validation of Pipelined Processors
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Refinement Maps for Efficient Verification of Processor Models
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
StressTest: an automatic approach to test generation via activity monitors
Proceedings of the 42nd annual Design Automation Conference
Test generation using SAT-based bounded model checking for validation of pipelined processors
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Distance-guided hybrid verification with GUIDO
Proceedings of the conference on Design, automation and test in Europe: Proceedings
An Integration of HOL and ACL2
FMCAD '06 Proceedings of the Formal Methods in Computer Aided Design
ACL2SIX: A Hint used to Integrate a Theorem Prover and an Automated Verification Tool
FMCAD '06 Proceedings of the Formal Methods in Computer Aided Design
Constraint-Based Verification
Combining Theorem Proving with Model Checking through Predicate Abstraction
IEEE Design & Test
Isabelle/HOL: a proof assistant for higher-order logic
Isabelle/HOL: a proof assistant for higher-order logic
A SAT-based decision procedure for the subclass of unrollable list formulas in ACL2 (SULFA)
IJCAR'06 Proceedings of the Third international joint conference on Automated Reasoning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An industrially effective environment for formal hardware verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A simple theorem prover based on symbolic trajectory evaluation and BDD's
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Enhancing bug hunting using high-level symbolic simulation
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Validating power architecture™ technology-based MPSoCs through executable specifications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimizing blocks in an SoC using symbolic code-statement reachability analysis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
A framework for testing hardware-software security architectures
Proceedings of the 26th Annual Computer Security Applications Conference
SAT-based semiformal verification of hardware
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
A framework for incremental modelling and verification of on-chip protocols
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
A monadic approach to automated reasoning for Bluespec SystemVerilog
Innovations in Systems and Software Engineering
Coverage-Directed Test Generation Automated by Machine Learning -- A Review
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Targeted random test generation for power-aware multicore designs
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
Formal verification methodology considerations for network on chips
Proceedings of the International Conference on Advances in Computing, Communications and Informatics
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The increasing size and complexity of industry hardware designs, along with stringent time-to-market requirements, have put a heavy burden on verification to ensure that designs are relatively bug free. A general theme successfully adopted by academia and several vendors is to apply multiple verification techniques so that they complement one another, resulting in an increase of the verification tool's overall effectiveness. Such integration must be carried out delicately and precisely so that the overall technique becomes more than merely a sum of the techniques. This article surveys the research that has taken place in this area.