Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
The turn model for adaptive routing
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Logic in computer science: modelling and reasoning about systems
Logic in computer science: modelling and reasoning about systems
Model checking
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
The Intel 4004 Microprocessor: What Constituted Invention?
IEEE Annals of the History of Computing
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Using Formal Techniques to Debug the AMBA System-on-Chip Bus Protocol
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
Computer Architecture, Fourth Edition: A Quantitative Approach
Computer Architecture, Fourth Edition: A Quantitative Approach
A Survey of Hybrid Techniques for Functional Verification
IEEE Design & Test
25 Years of Model Checking
Application Specific Routing Algorithms for Networks on Chip
IEEE Transactions on Parallel and Distributed Systems
Formal methods: Practice and experience
ACM Computing Surveys (CSUR)
Parallel explicit state reachability analysis and state space construction
ISPDC'03 Proceedings of the Second international conference on Parallel and distributed computing
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Use of Network on Chips (NoCs) as a flexible communication infrastructure is becoming a norm for designing advanced System on Chips (SoCs). However, their implementation complexity is enormous and use of industry proven functional verification methodologies start showing their limitations. Recent research activities have demonstrated that formal verification is capable of addressing most of the bottlenecks faced by functional verification techniques. In this context, this paper presents a survey on recent advances in the field of "Formally verifying a Network on Chip (NoC)". An overview of NoC design challenges is presented along with their formal verification methodologies. The paper concludes by highlighting that going forward, a Unified Formal Verification Methodology (UFVM) must be driven to ensure that the benefits of formal verification are reaped.