The existence of refinement mappings
Theoretical Computer Science
Proof-checking a data link protocol
TYPES '93 Proceedings of the international workshop on Types for proofs and programs
Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
Verifying timing properties of concurrent algorithms
Proceedings of the 7th IFIP WG6.1 International Conference on Formal Description Techniques VII
TYPES '94 Selected papers from the International Workshop on Types for Proofs and Programs
A Compositional Rule for Hardware Design Refinement
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
VDM '91 Proceedings of the 4th International Symposium of VDM Europe on Formal Software Development-Volume 2: Tutorials
XFM: An incremental methodology for developing formal models
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Survey of Hybrid Techniques for Functional Verification
IEEE Design & Test
A Formal Model of Clock Domain Crossing and Automated Verification of Time-Triggered Hardware
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
Transaction Based Modeling and Verification of Hardware Protocols
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
A functional formalization of on chip communications
Formal Aspects of Computing
A refinement approach to design and verification of on-chip communication protocols
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Incremental modelling and verification of the PCI express transaction layer
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
Isabelle/HOL: a proof assistant for higher-order logic
Isabelle/HOL: a proof assistant for higher-order logic
Hi-index | 0.00 |
Arguing formally about the correctness of on-chip communication protocols is an acknowledged verification challenge. We present a generic framework that tackles this problem using an incremental approach that interleaves model construction and verification. Our protocol models are based on abstract state machines formalized in Isabelle/HOL. We provide abstract building blocks and generic composition rules to support incremental addition of protocol features to a parameterized endpoint model. This structured approach controls model complexity. We can refine data structures and develop control independently, to create a concrete instantiation. To make the verification effort feasible, we combine interactive theorem proving with symbolic model checking using NuSMV. The theorem prover is used to reason about generic correctness properties of the abstract models given some local assumptions. We can use model checking to discharge these assumptions for a specific instantiation. We show the utility and breadth of the framework by sketching two case studies: modelling a bus protocol, and modelling the PCI Express point-to-point protocol.