Executable formal specification and validation of NoC communication infrastructures
Proceedings of the 21st annual symposium on Integrated circuits and system design
A generic implementation model for the formal verification of networks-on-chips
Proceedings of the Eighth International Workshop on the ACL2 Theorem Prover and its Applications
Formal validation of deadlock prevention in networks-on-chips
Proceedings of the Eighth International Workshop on the ACL2 Theorem Prover and its Applications
A formal approach to the verification of networks on chip
EURASIP Journal on Embedded Systems
Formal specification of networks-on-chips: deadlock and evacuation
Proceedings of the Conference on Design, Automation and Test in Europe
A framework for incremental modelling and verification of on-chip protocols
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Easy Formal Specification and Validation of Unbounded Networks-on-Chips Architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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This paper presents a formal model and a systematic approach to the validation of communication architectures at a high level of abstraction. This model is described mathematically by a function, named GeNoC. The correctness of GeNoC is expressed as a theorem, which states that messages emitted on the architecture reach their expected destination without any modification of their content. The model identifies the key constituents common to all on chip communication architectures, and their essential properties from which the correctness theorem is deduced. Each constituent is represented by a function that has no explicit definition but is constrained to satisfy the essential properties. Thus, the validation of a particular architecture is reduced to the proof that its concrete definition satisfies the essential properties. In practice, the model has been defined in the logic of the ACL2 theorem proving system. We illustrate our approach on several architectures that constitute concrete instances of the generic GeNoC model. Some of these applications come from industrial designs, such as the AMBA AHB bus or the Octagon network from ST Microelectronics.