Computer-Aided Reasoning: An Approach
Computer-Aided Reasoning: An Approach
Using Formal Techniques to Debug the AMBA System-on-Chip Bus Protocol
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
HERMES: an infrastructure for low area overhead packet-switching networks on chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Modeling layered distributed communication systems
Formal Aspects of Computing
Towards a formal theory of on chip communications in the ACL2 logic
ACL2 '06 Proceedings of the sixth international workshop on the ACL2 theorem prover and its applications
A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
A functional formalization of on chip communications
Formal Aspects of Computing
Deadlock prevention in the ÆTHEREAL protocol
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
A generic implementation model for the formal verification of networks-on-chips
Proceedings of the Eighth International Workshop on the ACL2 Theorem Prover and its Applications
Formal validation of deadlock prevention in networks-on-chips
Proceedings of the Eighth International Workshop on the ACL2 Theorem Prover and its Applications
Formal specification of networks-on-chips: deadlock and evacuation
Proceedings of the Conference on Design, Automation and Test in Europe
Easy Formal Specification and Validation of Unbounded Networks-on-Chips Architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A multi-level design methodology of multistage interconnection network for MPSOCs
International Journal of Computer Applications in Technology
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We describe an enhanced generic model for Networks-on-Chip (NoCs), implemented in the executable logic of the ACL2 theorem prover. The model is meant for serving as a formal reference for the specification, validation, and simulation at the initial design phase. Instantiated on a specific NoC, the model may be used for formal proofs and for simulation. The methodology is illustrated on HERMES.