Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
Introduction to algorithms
A universal proof technique for deadlock-free routing in interconnection networks
Proceedings of the seventh annual ACM symposium on Parallel algorithms and architectures
A General Theory for Deadlock Avoidance in Wormhole-Routed Networks
IEEE Transactions on Parallel and Distributed Systems
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Computer-Aided Reasoning: An Approach
Computer-Aided Reasoning: An Approach
A Necessary and Sufficient Condition for Deadlock-Free Adaptive Routing in Wormhole Networks
IEEE Transactions on Parallel and Distributed Systems
Using Formal Techniques to Debug the AMBA System-on-Chip Bus Protocol
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
HERMES: an infrastructure for low area overhead packet-switching networks on chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Towards a formal theory of on chip communications in the ACL2 logic
ACL2 '06 Proceedings of the sixth international workshop on the ACL2 theorem prover and its applications
Electronic Notes in Theoretical Computer Science (ENTCS)
A tool for automatic detection of deadlock in wormhole networks on chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A functional formalization of on chip communications
Formal Aspects of Computing
Executable formal specification and validation of NoC communication infrastructures
Proceedings of the 21st annual symposium on Integrated circuits and system design
A formal approach to the verification of networks on chip
EURASIP Journal on Embedded Systems
Deadlock prevention in the ÆTHEREAL protocol
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Verifying deadlock-freedom of communication fabrics
VMCAI'11 Proceedings of the 12th international conference on Verification, model checking, and abstract interpretation
Challenges in verifying communication fabrics
ITP'11 Proceedings of the Second international conference on Interactive theorem proving
Easy Formal Specification and Validation of Unbounded Networks-on-Chips Architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A formal proof of a necessary and sufficient condition for deadlock-free adaptive networks
ITP'10 Proceedings of the First international conference on Interactive Theorem Proving
Scalable progress verification in credit-based flow-control systems
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.02 |
Networks-on-chips (NoC) are emerging as a promising interconnect solution for efficient Multi-Processors Systems-on-Chips. We propose a methodology that supports the specification of parametric NoCs. We provide sufficient constraints that ensure deadlock-free routing, functional correctness, and liveness of the design. To illustrate our method, we discharge these constraints for a parametric NoC inspired by the HERMES architecture.