Interconnection networks for high-performance parallel computers
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
An Efficient Algorithm for Finding Structural Deadlocks in Colored Petri Nets
Proceedings of the 14th International Conference on Application and Theory of Petri Nets
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Efficient reduction of finite state model checking to reachability analysis
International Journal on Software Tools for Technology Transfer (STTT)
Formal specification of networks-on-chips: deadlock and evacuation
Proceedings of the Conference on Design, Automation and Test in Europe
SAT-based model checking without unrolling
VMCAI'11 Proceedings of the 12th international conference on Verification, model checking, and abstract interpretation
Verifying deadlock-freedom of communication fabrics
VMCAI'11 Proceedings of the 12th international conference on Verification, model checking, and abstract interpretation
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
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Formal verification of liveness properties of practical communication fabrics are generally intractable with present day verification tools. We focus on a particular type of liveness called 'progress' which is a form of deadlock freedom. An end-to-end progress property is broken down into localized safety assertions, which are more easily provable, and lead to a formal proof of progress. Our target systems are credit-based flow-control networks. We present case studies of this type and experimental results of progress verification of large networks using a bit-level formal verifier.