A Necessary and Sufficient Condition for Deadlock-Free Adaptive Routing in Wormhole Networks
IEEE Transactions on Parallel and Distributed Systems
Circular Compositional Reasoning about Liveness
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
An Efficient Algorithm for Finding Structural Deadlocks in Colored Petri Nets
Proceedings of the 14th International Conference on Application and Theory of Petri Nets
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
A tool for automatic detection of deadlock in wormhole networks on chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Algorithmic Analysis of Piecewise FIFO Systems
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
Automatic verification of safety and liveness for pipelined machines using WEB refinement
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proving that non-blocking algorithms don't block
Proceedings of the 36th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Formal specification of networks-on-chips: deadlock and evacuation
Proceedings of the Conference on Design, Automation and Test in Europe
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
Deadlock prevention in the ÆTHEREAL protocol
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Challenges in verifying communication fabrics
ITP'11 Proceedings of the Second international conference on Interactive theorem proving
Hunting deadlocks efficiently in microarchitectural models of communication fabrics
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
Formal Methods in System Design
Towards the formal verification of cache coherency at the architectural level
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
Scalable progress verification in credit-based flow-control systems
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Avoiding message dependent deadlocks in communication fabrics is critical for modern microarchitectures. If discovered late in the design cycle, deadlocks lead to missed project deadlines and suboptimal design decisions. One approach to avoid this problem is to get high level of confidence on an early microarchitectural model. However, formal proofs of liveness even on abstract models are hard due to large number of queues and distributed control. In this work we address liveness verification of communication fabrics described in the form of high-level microarchitectural models which use a small set of well-defined primitives. We prove that under certain realistic restrictions, deadlock freedom can be reduced to unsatisfiability of a system of Boolean equations. Using this approach, we have automatically verified liveness of several non-trivial models (derived from industrial microarchitectures), where state-of-theart model checkers failed and pen and paper proofs were either tedious or unknown.