Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
Formal development of NoC systems in B
Nordic Journal of Computing - Selected papers of the 17th nordic workshop on programming theory (NWPT'05), October 19-21, 2005
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ACL2 '06 Proceedings of the sixth international workshop on the ACL2 theorem prover and its applications
Executable formal specification and validation of NoC communication infrastructures
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Formal validation of deadlock prevention in networks-on-chips
Proceedings of the Eighth International Workshop on the ACL2 Theorem Prover and its Applications
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EURASIP Journal on Embedded Systems
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
The connection-then-credit flow control protocol for heterogeneous multicore systems-on-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Formal specification of networks-on-chips: deadlock and evacuation
Proceedings of the Conference on Design, Automation and Test in Europe
A TDM slot allocation flow based on multipath routing in NoCs
Microprocessors & Microsystems
Verifying deadlock-freedom of communication fabrics
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ACM Transactions on Design Automation of Electronic Systems (TODAES)
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ACM Transactions on Architecture and Code Optimization (TACO)
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The Æthereal protocol enables both guaranteed and best effort communication in an on-chip packet switching network. We discuss a formal specification of Æthereal and its underlying network in terms of the PVS specification language. Using PVS we prove absence of deadlock for an abstract version of our model.