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Principles and Practices of Interconnection Networks
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A generic network on chip model
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A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study
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A refinement approach to design and verification of on-chip communication protocols
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Formal validation of deadlock prevention in networks-on-chips
Proceedings of the Eighth International Workshop on the ACL2 Theorem Prover and its Applications
Incremental modelling and verification of the PCI express transaction layer
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
Formal specification of networks-on-chips: deadlock and evacuation
Proceedings of the Conference on Design, Automation and Test in Europe
Incremental and verified modeling of the PCI express protocol
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
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A multi-level design methodology of multistage interconnection network for MPSOCs
International Journal of Computer Applications in Technology
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This paper is devoted to the expression for a formal theory of communication networks in the ACL2 logic. More precisely, we have developed a generic model called GeNoC, in a general mathematical notation, with the use of quantification over variables as well as over functions. We present here its expression in the first order quantifier free logic of the ACL2 theorem prover. We describe our systematic approach to cast it into ACL2, especially how we use the encapsulation principle to obtain a systematic methodology to specify and validate on chip communications architectures. We summarize the different instances of GeNoC developed so far in ACL2, some come from industrial designs. We illustrate our approach on an XY routing algorithm.