A New Theory of Deadlock-Free Adaptive Routing in Wormhole Networks
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Parallel and Distributed Systems
A General Theory for Deadlock Avoidance in Wormhole-Routed Networks
IEEE Transactions on Parallel and Distributed Systems
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Bounds on evacuation time for deflection routing
Distributed Computing
Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
Towards a formal theory of on chip communications in the ACL2 logic
ACL2 '06 Proceedings of the sixth international workshop on the ACL2 theorem prover and its applications
A Necessary and Sufficient Condition for Deadlock-Free Adaptive Routing in Wormhole Networks
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
A tool for automatic detection of deadlock in wormhole networks on chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Mechanical Analysis of Program Verification Strategies
Journal of Automated Reasoning
A functional formalization of on chip communications
Formal Aspects of Computing
Executable formal specification and validation of NoC communication infrastructures
Proceedings of the 21st annual symposium on Integrated circuits and system design
A generic implementation model for the formal verification of networks-on-chips
Proceedings of the Eighth International Workshop on the ACL2 Theorem Prover and its Applications
Deadlock prevention in the ÆTHEREAL protocol
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
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Complex systems-on-chips (SoCs) are built as the assembly of pre-designed parameterized components. The specification and validation of the communication infrastructure becomes a crucial step in the early phase of any SoC design. The Generic Network-on-Chip model (GeNoC) has been recently proposed as a generic specification environment, restricted to safety properties. We report on an initial extension of the GeNoC model with a generic termination condition and a generic property showing the prevention of livelock and deadlock. The latter shows that all messages injected in the network eventually reach their destination for all possible values of network parameters like topology, size of the network, message length or injection time. We illustrate our initial results with the validation of a circuit switching technique.