Experience with chisl, a configurable hierarchical interface specification language
Computer Graphics Forum
Verification of electronic systems
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Code generation and analysis for the functional verification of micro processors
DAC '96 Proceedings of the 33rd annual Design Automation Conference
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Formal verification of embedded systems based on CFSM networks
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Simulation Model Design and Execution: Building Digital Worlds
Simulation Model Design and Execution: Building Digital Worlds
Grammar-based Hardware Synthesis of Data Communication Protocols
ISSS '96 Proceedings of the 9th international symposium on System synthesis
Analysis and Synthesis of Concurrent Digital Systems Using Control-Flow Expressions
Analysis and Synthesis of Concurrent Digital Systems Using Control-Flow Expressions
A New Interface Specification Methodology and
A New Interface Specification Methodology and
Automatic synthesis of interfaces between incompatible protocols
DAC '98 Proceedings of the 35th annual Design Automation Conference
Design and specification of embedded systems in Java using successive, formal refinement
DAC '98 Proceedings of the 35th annual Design Automation Conference
System-level exploration with SpecSyn
DAC '98 Proceedings of the 35th annual Design Automation Conference
A case study on modeling shared memory access effects during performance analysis of HW/SW systems
Proceedings of the 6th international workshop on Hardware/software codesign
Communication synthesis for distributed embedded systems
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Interface synthesis: a vertical slice from digital logic to software components
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Communication refinement in video systems on chip
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Fast hardware-software co-simulation using VHDL models
DATE '99 Proceedings of the conference on Design, automation and test in Europe
ipChinook: an integrated IP-based design framework for distributed embedded systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Application of high level interface-based design to telecommunications system hardware
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Synthesis and optimization of coordination controllers for distributed embedded systems
Proceedings of the 37th Annual Design Automation Conference
Fast performance analysis of bus-based system-on-chip communication architectures
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Techniques for reducing read latency of core bus wrappers
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Standards for system-level design: practical reality or solution in search of a question?
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
Mixed-level cosimulation for fine gradual refinement of communication in SoC design
Proceedings of the conference on Design, automation and test in Europe
Design methodologies for system level IP
Proceedings of the conference on Design, automation and test in Europe
Design technology productivity in the DSM era (invited talk)
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A generic wrapper architecture for multi-processor SoC cosimulation and design
Proceedings of the ninth international symposium on Hardware/software codesign
On-chip communication architecture for OC-768 network processors
Proceedings of the 38th annual Design Automation Conference
Control and communication performance analysis of embedded DSP systems in the MASIC methodology
Proceedings of the 14th international symposium on Systems synthesis
Experiments with the peripheral virtual component interface
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Prefetching for improved bus wrapper performance in cores
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automatic generation of embedded memory wrapper for multiprocessor SoC
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
Traffic analysis for on-chip networks design of multimedia applications
Proceedings of the 39th annual Design Automation Conference
Unifying memory and processor wrapper architecture in multiprocessor SoC design
Proceedings of the 15th international symposium on System Synthesis
Formal verification in a component-based reuse methodology
Proceedings of the 15th international symposium on System Synthesis
An object-oriented design process for system-on-chip using UML
Proceedings of the 15th international symposium on System Synthesis
Challenges and opportunities in broadband and wireless communication designs
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Efficient exploration of the SoC communication architecture design space
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Formal Models for Embedded System Design
IEEE Design & Test
A Metamodel for Studying Concepts in Electronic System Design
IEEE Design & Test
Structured Component Composition Frameworks for Embedded System Design
HiPC '02 Proceedings of the 9th International Conference on High Performance Computing
Formal Models for Communication-Based Design
CONCUR '00 Proceedings of the 11th International Conference on Concurrency Theory
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Mixing ATPG and property checking for testing HW/SW interfaces
Proceedings of the 13th ACM Great Lakes symposium on VLSI
A hierarchical modeling framework for on-chip communication architectures
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Design flow for HW / SW acceleration transparency in the thumbpod secure embedded system
Proceedings of the 40th annual Design Automation Conference
Automatic communication refinement for system level design
Proceedings of the 40th annual Design Automation Conference
Multi-Level Communication Synthesis of Heterogeneous Multilanguage Specification
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Synthesis Experiments and Performance Metrics for Evaluating the Quality of IP Blocks and Megacells
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Pre-Fetching for Improved Core Interfacing
Proceedings of the 12th international symposium on System synthesis
SystemC
Will networks on chip close the productivity gap?
Networks on chip
An IP-based on-chip packet-switched network
Networks on chip
Fault Models and Test Generation for Hardware-Software Covalidation
IEEE Design & Test
A modular simulation framework for architectural exploration of on-chip interconnection networks
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Analyzing On-Chip Communication in a MPSoC Environment
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Proceedings of the conference on Design, automation and test in Europe - Volume 2
OCCN: a NoC modeling framework for design exploration
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
On-chip traffic modeling and synthesis for MPEG-2 video applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Extending the transaction level modeling approach for fast communication architecture exploration
Proceedings of the 41st annual Design Automation Conference
System design for DSP applications in transaction level modeling paradigm
Proceedings of the 41st annual Design Automation Conference
Bandwidth tracing arbitration algorithm for mixed-clock SoC with dynamic priority adaptation
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Design and programming of embedded multiprocessors: an interface-centric approach
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Efficient exploration of on-chip bus architectures and memory allocation
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
IPSIM: SystemC 3.0 Enhancements for Communication Refinement
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Strategies for the integration of hardware and software IP components in embedded systems-on-chip
Integration, the VLSI Journal - Special issue: IP and design reuse
Issues in the development of a practical NoC: the Proteo concept
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Run-time support for heterogeneous multitasking on reconfigurable SoCs
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Retargetable generation of TLM bus interfaces for MP-SoC platforms
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Systematic Approach to Exploring Embedded System Architectures at Multiple Abstraction Levels
IEEE Transactions on Computers
An automatic interconnection rectification technique for SoC design integration
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A processor core synthesis system in IP-based SoC design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Model-centric software architecture reconstruction
Software—Practice & Experience
COSMECA: application specific co-synthesis of memory and communication architectures for MPSoC
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A formal method for hardware IP design and integration under I/O and timing constraints
ACM Transactions on Embedded Computing Systems (TECS)
Structural component composition for system-level models
Formal methods and models for system design
System level design paradigms: Platform-based design and communication synthesis
Proceedings of the 41st annual Design Automation Conference
A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Towards a formal theory of on chip communications in the ACL2 logic
ACL2 '06 Proceedings of the sixth international workshop on the ACL2 theorem prover and its applications
Constrained algorithmic IP design for system-on-chip
Integration, the VLSI Journal
A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Hardware/software IP integration using the ROSES design environment
ACM Transactions on Embedded Computing Systems (TECS)
System-level design flow based on a functional reference for HW and SW
Proceedings of the 44th annual Design Automation Conference
Proceedings of the 44th annual Design Automation Conference
A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH
ACM Transactions on Embedded Computing Systems (TECS)
Fast exploration of bus-based communication architectures at the CCATB abstraction
ACM Transactions on Embedded Computing Systems (TECS)
Active control and digital rights management of integrated circuit IP cores
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
Dynamically configurable bus topologies for high-performance on-chip communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Signal Processing Systems
Co-simulation and communication synthesis approach for intellectual properties based SoCs
Computers and Electrical Engineering
Towards a synthesis semantics for systemC channels
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Efficient exploration of bus-based system-on-chip architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A generic network on chip model
TPHOLs'05 Proceedings of the 18th international conference on Theorem Proving in Higher Order Logics
ESL Design and Verification: A Prescription for Electronic System Level Methodology
ESL Design and Verification: A Prescription for Electronic System Level Methodology
EDA for secure and dependable cybercars: challenges and opportunities
Proceedings of the 49th Annual Design Automation Conference
From 1G to 10G: code reuse in action
Proceedings of the first edition workshop on High performance and programmable networking
Automatic generation of high-speed accurate TLM models for out-of-order pipelined bus
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on ESTIMedia'10
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A new system design methodology is proposed that separates communicationfrom behavior. To demonstrate the methodology weapplied it to a simple ATM design. Since verification is clearly amajor stumbling block for large system design, we focussed on theverification aspects of our methodology.In particular, a simulator was developed that is based on the communicationparadigm typical of our methodology. The simulatorgives substantial performance improvements without sacrificinguser access to detail.Finally, the potential for this methodology to improve verification,modeling and synthesis is explored.