DAC '97 Proceedings of the 34th annual Design Automation Conference
Communication synthesis and HW/SW integration for embedded system design
Proceedings of the 6th international workshop on Hardware/software codesign
Proceedings of the 38th annual Design Automation Conference
System Design: A Practical Guide with Specc
System Design: A Practical Guide with Specc
Unifying memory and processor wrapper architecture in multiprocessor SoC design
Proceedings of the 15th international symposium on System Synthesis
An Object-Oriented Communication Library for Hardware-Software CoDesign
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
Automatic generation of bus functional models from transaction level models
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Automatic network generation for system-on-chip communication design
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A Systematic Approach to Exploring Embedded System Architectures at Multiple Abstraction Levels
IEEE Transactions on Computers
System-level communication modeling for network-on-chip synthesis
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
TRAIN: a virtual transaction layer architecture for TLM-based HW/SW codesign of synthesizable MPSoC
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Rapid-prototyping emulation system co-emulation modelling interface for systemC real-time emulation
ICS'08 Proceedings of the 12th WSEAS international conference on Systems
Towards a synthesis semantics for systemC channels
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Hardware/software co-design environment for hierarchical platform-based design
CSCWD'04 Proceedings of the 8th international conference on Computer Supported Cooperative Work in Design I
A case for visualization-integrated system-level design space exploration
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
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This paper presents a methodology and algorithms for automatic communication refinement. The communication refinement task in system-level synthesis transforms abstract data-transfer between components to its actual bus level implementation. The input model of the communication refinement is a set of concurrently executing components, communicating with each other through abstract communication channels. The refined model reflects the actual communication architecture. Choosing a good communication architecture in system level designs requires sufficient exploration through evaluation of various architectures. However, this would not be possible with manually refining the system model for each communication architecture. For one, manual refinement is tedious and error-prone. Secondly, it wastes substantial amount of precious designer time. We solve this problem with automatic model refinement. We also present a set of experimental results to demonstrate how the proposed approach works on a typical system level design.