Unifying memory and processor wrapper architecture in multiprocessor SoC design

Authors:
Férid Gharsalli;Damien Lyonnard;Samy Meftali;Frédéric Rousseau;Ahmed A. Jerraya
Affiliations:
Laboratoire TIMA, Grenoble cedex, France;Laboratoire TIMA, Grenoble cedex, France;Laboratoire TIMA, Grenoble cedex, France;Laboratoire TIMA, Grenoble cedex, France;Laboratoire TIMA, Grenoble cedex, France
Venue:
Proceedings of the 15th international symposium on System Synthesis
Year:
2002

Citing 12
Cited 4

Computer organization & design: the hardware/software interface

Computer organization & design: the hardware/software interface
Constructing application-specific heterogeneous embedded architectures from custom HW/SW applications

DAC '96 Proceedings of the 33rd annual Design Automation Conference
Interface-based design

DAC '97 Proceedings of the 34th annual Design Automation Conference
COSY communication IP's

Proceedings of the 37th Annual Design Automation Conference
Standards for system-level design: practical reality or solution in search of a question?

DATE '00 Proceedings of the conference on Design, automation and test in Europe
Methodology for hardware/software co-verification in C/C++ (short paper)

ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Scalable and flexible cosimulation of SoC designs with heterogeneous multi-processor target architectures

Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A generic wrapper architecture for multi-processor SoC cosimulation and design

Proceedings of the ninth international symposium on Hardware/software codesign
Automatic generation of application-specific architectures for heterogeneous multiprocessor system-on-chip

Proceedings of the 38th annual Design Automation Conference
Synthesis of pipelined memory access controllers for streamed data applications on FPGA-based computing engines

Proceedings of the 14th international symposium on Systems synthesis
Automatic generation of embedded memory wrapper for multiprocessor SoC

Proceedings of the 39th annual Design Automation Conference
Parallel Computer Architecture: A Hardware/Software Approach

Parallel Computer Architecture: A Hardware/Software Approach

Automatic communication refinement for system level design

Proceedings of the 40th annual Design Automation Conference
Reusable component IP design using refinement-based design environment

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Performance evaluation and optimization of dual-port SDRAM architecture for mobile embedded systems

CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Concept-based partitioning for large multidomain multifunctional embedded systems

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper, we present a new methodology for application specific multiprocessor system-on-chip design. This approach facilitates the integration of existing components with the concept of wrapper. Wrappers allow automatic adaptation of physical interfaces to a communication network. We also give a generic architecture to produce these wrappers, either for processors or for other specific components such as memory IP. This approach has successfully been applied on a low-level image processing application.