T: a multithreaded massively parallel architecture
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
The Stanford FLASH multiprocessor
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Co-design of interleaved memory systems
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Designing systems-on-chip using cores
Proceedings of the 37th Annual Design Automation Conference
Proceedings of the 37th Annual Design Automation Conference
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Memory arbitration and cache management in stream-based systems
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Standards for system-level design: practical reality or solution in search of a question?
DATE '00 Proceedings of the conference on Design, automation and test in Europe
An efficient architecture model for systematic design of application-specific multiprocessor SoC
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
Stream communication between real-time tasks in a high-performance multiprocessor
Proceedings of the conference on Design, automation and test in Europe
Experiments with the peripheral virtual component interface
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Parallel Computer Architecture: A Hardware/Software Approach
Parallel Computer Architecture: A Hardware/Software Approach
PROPHID: a heterogeneous multi-processor architecture for multimedia
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
A generic wrapper architecture for multi-processor SoC cosimulation and design
Proceedings of the ninth international symposium on Hardware/software codesign
An optimal memory allocation for application-specific multiprocessor system-on-chip
Proceedings of the 14th international symposium on Systems synthesis
Automatic generation of embedded memory wrapper for multiprocessor SoC
Proceedings of the 39th annual Design Automation Conference
Component-based design approach for multicore SoCs
Proceedings of the 39th annual Design Automation Conference
Unifying memory and processor wrapper architecture in multiprocessor SoC design
Proceedings of the 15th international symposium on System Synthesis
System-level abstraction semantics
Proceedings of the 15th international symposium on System Synthesis
Colif: A Design Representation for Application-Specific Multiprocessor SOCs
IEEE Design & Test
Multiprocessor SoC Platforms: A Component-Based Design Approach
IEEE Design & Test
Multi-Level Modeling of Software on Hardware in Concurrent Computation
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
The design context of concurrent computation systems
Proceedings of the tenth international symposium on Hardware/software codesign
Application of design patterns for hardware design
Proceedings of the 40th annual Design Automation Conference
Automatic communication refinement for system level design
Proceedings of the 40th annual Design Automation Conference
RSP '01 Proceedings of the 12th International Workshop on Rapid System Prototyping
A scalable single-chip multi-processor architecture with on-chip RTOS kernel
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Synthesis and verification
Unified Component Integration Flow for Multi-Processor SoC Design and Validation
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Supporting Cache Coherence in Heterogeneous Multiprocessor Systems
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Journal of Systems and Software - Special issue: Rapid system prototyping
Automatic generation of bus functional models from transaction level models
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Automated Bus Generation for Multiprocessor SoC Design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Strategies for the integration of hardware and software IP components in embedded systems-on-chip
Integration, the VLSI Journal - Special issue: IP and design reuse
Floorplan-aware automated synthesis of bus-based communication architectures
Proceedings of the 42nd annual Design Automation Conference
Automatic network generation for system-on-chip communication design
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A comparison of the RTU hardware RTOS with a hardware/software RTOS
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Automated throughput-driven synthesis of bus-based communication architectures
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
System-Level Design Methodology with Direct Execution For Multiprocessors on SoPC
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Affinity-Driven System Design Exploration for Heterogeneous Multiprocessor SoC
IEEE Transactions on Computers
Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint
Proceedings of the 43rd annual Design Automation Conference
FABSYN: floorplan-aware bus architecture synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automatic generation of transaction level models for rapid design space exploration
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Challenges in exploitation of loop parallelism in embedded applications
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Multi-processor system design with ESPAM
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Hardware/software IP integration using the ROSES design environment
ACM Transactions on Embedded Computing Systems (TECS)
MOCDEX: multiprocessor on chip multiobjective design space exploration with direct execution
EURASIP Journal on Embedded Systems
A framework for rapid system-level exploration, synthesis, and programming of multimedia MP-SoCs
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Three-dimensional multiprocessor system-on-chip thermal optimization
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Application-aware snoop filtering for low-power cache coherence in embedded multiprocessors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Simultaneous on-chip bus synthesis and voltage scaling under random on-chip data traffic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Daedalus: toward composable multimedia MP-SoC design
Proceedings of the 45th annual Design Automation Conference
Slack allocation based co-synthesis and optimization of bus and memory architectures for MPSoCs
Proceedings of the conference on Design, automation and test in Europe
Tool Integration and Interoperability Challenges of a System-Level Design Flow: A Case Study
SAMOS '08 Proceedings of the 8th international workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
On the exploitation of loop-level parallelism in embedded applications
ACM Transactions on Embedded Computing Systems (TECS)
System-on-chip environment: a SpecC-based framework for heterogeneous MPSoC design
EURASIP Journal on Embedded Systems - C-Based Design of Heterogeneous Embedded Systems
Microprocessors & Microsystems
A generic network interface architecture for a networked processor array (NePA)
ARCS'08 Proceedings of the 21st international conference on Architecture of computing systems
Journal of Systems Architecture: the EUROMICRO Journal
Designing heterogeneous embedded network-on-chip platforms with users in mind
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
User-centric design space exploration for heterogeneous network-on-chip platforms
Proceedings of the Conference on Design, Automation and Test in Europe
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
We present a design flow for the generation of application-specific multiprocessor architectures. In the flow, architectural parameters are first extracted from a high-level system specification. Parameters are used to instantiate architectural components, such as processors, memory modules and communication networks. The flow includes the automatic generation of communication coprocessor that adapts the processor to the communication network in an application-specific way. Experiments with two system examples show the effectiveness of the presented design flow.