Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Superlog, a unified design language for system-on-chip
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
An efficient architecture model for systematic design of application-specific multiprocessor SoC
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 38th annual Design Automation Conference
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Pattern-based verification of connections to intellectual property cores
Integration, the VLSI Journal
Proceedings of the conference on Design, automation and test in Europe - Volume 1
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Automated Bus Generation for Multiprocessor SoC Design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
System Level Specification in Lava
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Strategies for the integration of hardware and software IP components in embedded systems-on-chip
Integration, the VLSI Journal - Special issue: IP and design reuse
VCore-based design methodology
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Hardware/software co-design using hierarchical platform-based design method
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Hardware/software IP integration using the ROSES design environment
ACM Transactions on Embedded Computing Systems (TECS)
Proceedings of the 20th annual conference on Integrated circuits and systems design
Dynamic task allocation strategies in MPSoC for soft real-time applications
Proceedings of the conference on Design, automation and test in Europe
Concept-based partitioning for large multidomain multifunctional embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
RF authenticated reconfiguration-based access control protection scheme for SRAM-based FPGA IP cores
International Journal of Electronic Security and Digital Forensics
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Leading-edge systems-on-chip (SoC) being designed today could reach 20 Million gates and 0.5 to 1 GHz operating frequency. In order to implement such systems, designers are increasingly relying on reuse of Intellectual property (IP) blocks. Since IP blocks are pre-designed and pre-verified, the designer can concentrate on the complete system without having to worry about the correctness or performance of the individual components. That is the goal, in theory. In practice, assembling on SoC using IP blocks is still an error-prone, labor-intensive and time-consuming process. This paper discusses the main challenges in SoC designs using IP blocks and elaborates on the methodology and tools being put in place at IBM for addressing the problem. It explains IBM's SoC architecture and gives algorithmic details on the high-level tools being developed for SoC design.