Intellectual property protection in the EDA industry
DAC '94 Proceedings of the 31st annual Design Automation Conference
Designing systems-on-chip using cores
Proceedings of the 37th Annual Design Automation Conference
Secure Configuration of Field Programmable Gate Arrays
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Cryptography and Network Security (4th Edition)
Cryptography and Network Security (4th Edition)
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
An automated, FPGA-based reconfigurable, low-power RFID tag
Microprocessors & Microsystems
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
RF authenticated protection scheme for SRAM-based FPGA IP cores
International Journal of Electronic Security and Digital Forensics
Partial-encryption technique for intellectual property protection of FPGA-based products
IEEE Transactions on Consumer Electronics
The age of intellectual property
IEEE Communications Magazine
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The constantly growing demand for ready to use design components, also known as intellectual property IP cores, has created a very lucrative and flourishing market which is very likely to continue its current path not only into the near future. With increase in use of field programmable gate arrays FPGAs in production designs, and with growth of system on FPGA SOF applications, the security of FPGA IP cores cannot be taken for granted anymore. In this paper, we have proposed a novel wireless-based IP core infringement preventive approach for intellectual property protection IPP of static random access memory SRAM-based FPGA IP cores. The proposed scheme exploits reconfiguration aspect of SRAM-based FPGA and incorporates special tag bypass features for increase suitability of proposed scheme as an IPP technique for reconfigurable IP cores. A hardware prototype is developed for evaluation of proposed scheme and the testing results are quite encouraging.