Intellectual property protection in the EDA industry
DAC '94 Proceedings of the 31st annual Design Automation Conference
Cryptographic rights management of FPGA intellectual property cores
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Secure Configuration of Field Programmable Gate Arrays
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
An automated, FPGA-based reconfigurable, low-power RFID tag
Microprocessors & Microsystems
Power Signature Watermarking of IP Cores for FPGAs
Journal of Signal Processing Systems
Offline hardware/software authentication for reconfigurable platforms
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Read-proof hardware from protective coatings
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Partial-encryption technique for intellectual property protection of FPGA-based products
IEEE Transactions on Consumer Electronics
RF authenticated reconfiguration-based access control protection scheme for SRAM-based FPGA IP cores
International Journal of Electronic Security and Digital Forensics
RFID based access control protection scheme for SRAM FPGA IP cores
Microprocessors & Microsystems
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Field programmable gate arrays (FPGAs) have become increasingly popular due to their rapid development times and low costs. Many FPGA-based systems utilise third-party intellectual property (IP) in their development. With their increased use, the need to protect the IP against unauthorised use has become important. In this paper, we have proposed a novel wireless intellectual property protection (IPP) technique that overcomes the secure secret decryption key storage problem associated with traditional encryption-based IPP techniques that are widely used for IPP of static random access memory-based FPGA IP cores. The proposed scheme also provides an extra authentication protection for IP cores to make it more security efficient. The results derived from the testing of hardware prototype used for the evaluation of the proposed scheme are quite encouraging.