The Unified Modeling Language reference manual
The Unified Modeling Language reference manual
Energy-conserving access protocols for identification networks
IEEE/ACM Transactions on Networking (TON)
Embedded UML: a merger of real-time UML and co-design
Proceedings of the ninth international symposium on Hardware/software codesign
JADE: An Embedded Systems Specification, Code Generation and Optimization Tool
SBCCI '00 Proceedings of the 13th symposium on Integrated circuits and systems design
RSP '00 Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000)
SPARK: A High-Lev l Synthesis Framework For Applying Parallelizing Compiler Transformations
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Software Power Estimation and Optimization for High Performance, 32-bit Embedded Processors
ICCD '98 Proceedings of the International Conference on Computer Design
XTREM: a power simulator for the Intel XScale® core
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Proceedings of the 2004 international symposium on Low power electronics and design
Modeling event driven applications with a specification language (MEDASL)
OOPSLA '04 Companion to the 19th annual ACM SIGPLAN conference on Object-oriented programming systems, languages, and applications
Privacy and security in library RFID: issues, practices, and architectures
Proceedings of the 11th ACM conference on Computer and communications security
LANDMARC: indoor location sensing using active RFID
Wireless Networks - Special issue: Pervasive computing and communications
An FPGA-based VLIW processor with custom hardware execution
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Reducing power while increasing performance with supercisc
ACM Transactions on Embedded Computing Systems (TECS)
EURASIP Journal on Applied Signal Processing
An automated, reconfigurable, low-power RFID tag
Proceedings of the 43rd annual Design Automation Conference
A design automation and power estimation flow for RFID systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Implementation and performance evaluation of an active RFID system for fast tag collection
Computer Communications
RF authenticated protection scheme for SRAM-based FPGA IP cores
International Journal of Electronic Security and Digital Forensics
Evaluation and exploration of RFID systems by rapid prototyping
Personal and Ubiquitous Computing
Time-interleaved CMOS chip design of Manchester and Miller encoder for RFID application
Analog Integrated Circuits and Signal Processing
RF authenticated reconfiguration-based access control protection scheme for SRAM-based FPGA IP cores
International Journal of Electronic Security and Digital Forensics
RFID based access control protection scheme for SRAM FPGA IP cores
Microprocessors & Microsystems
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The use of radio frequency identification (RFID) technology is expanding rapidly in numerous applications such as logistics, supply chain management, transportation, healthcare and aviation. Due to the variety of the current applications, typical RFID systems use application specific hardware and proprietary protocols. These systems generally have long design times, no tolerance to changes in application or standard, and hence very high system costs. This paper describes an RFID tag specification and automated design flow for the creation of customized, low-power, active RFID tags. RFID primitives supported by the tag are enumerated with assembly like RFID macros. From these macros, the RFID pre-processor generates templates automatically. The behavior of each RFID primitive is specified using ANSI C where indicated within the template. The resulting file is compiled by the RFID compiler for the extensible tag. In order to save power, a smart buffer has been developed to sit between the transceiver and the tag controller. Because RFID packets are broadcast to everyone in range, the smart buffer contains minimal logic to detect whether incoming packets are intended for the tag. By doing so, the main controller may remain powered down to reduce system power consumption. Two System-on-a-Chip implementation strategies are presented. First, a microprocessor based system for which a C program is automatically generated and compiled for the system. The second replaces the microprocessor with a block of low-power FPGA logic. The user supplied RFID logic is specified in RFID macros and ANSI-C and automatically converted into combinational VHDL by the RFID compiler. Based on a test program, the processors required 183, 43, and 19@mJ per transaction for StrongARM, XScale, and EISC processors, respectively. By replacing the processor with a Coolrunner II, the controller can be reduced to 1.11nJ per transaction.