Energy-conserving access protocols for identification networks
IEEE/ACM Transactions on Networking (TON)
Software Power Estimation and Optimization for High Performance, 32-bit Embedded Processors
ICCD '98 Proceedings of the International Conference on Computer Design
XTREM: a power simulator for the Intel XScale® core
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Proceedings of the 2004 international symposium on Low power electronics and design
Modeling event driven applications with a specification language (MEDASL)
OOPSLA '04 Companion to the 19th annual ACM SIGPLAN conference on Object-oriented programming systems, languages, and applications
LANDMARC: indoor location sensing using active RFID
Wireless Networks - Special issue: Pervasive computing and communications
An FPGA-based VLIW processor with custom hardware execution
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Reducing power while increasing performance with supercisc
ACM Transactions on Embedded Computing Systems (TECS)
An automated, FPGA-based reconfigurable, low-power RFID tag
Microprocessors & Microsystems
EURASIP Journal on Applied Signal Processing
A 915 MHz UHF low power RFID tag
Proceedings of the 20th annual conference on Integrated circuits and systems design
Radio frequency identification prototyping
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A design automation and power estimation flow for RFID systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A self-calibrated DLL-based clock generator for an energy-aware EISC processor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper describes an ultra low power active RFID tag and its automated design flow. RFID primitives to be supported by the tag are enumerated with RFID macros and the behavior of each primitive is specified using ANSI-C within the template to automatically generate the tag controller. Two power saving components, a passive transceiver/burst switch and a smart buffer, are presented to save power and increase tag lifetime. Based on a test program, the processors required 183, 43, and 19 μ&J per transaction for StrongARM, XScale, and EISC processors, respectively. Three hardware controllers using a Fusion FPGA, Coolrunner II CPLD, and ASIC required 13 nJ, 1.3 nJ, and 0.07 nJ per transaction.