The design and use of simplepower: a cycle-accurate energy estimation tool
Proceedings of the 37th Annual Design Automation Conference
Quantifying the energy consumption of a pocket computer and a Java virtual machine
Proceedings of the 2000 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Energy-driven integrated hardware-software optimizations using SimplePower
Proceedings of the 27th annual international symposium on Computer architecture
Cycle-accurate energy measurement and characterization with a case study of the ARM7TDMI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Profile guided selection of ARM and thumb instructions
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
Runtime Power Monitoring in High-End Processors: Methodology and Empirical Data
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
Transition aware scheduling: increasing continuous idle-periods in resource units
Proceedings of the 2nd conference on Computing frontiers
Coordinated, distributed, formal energy management of chip multiprocessors
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Power prediction for intel XScale® processors using performance monitoring unit events
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Aggregating processor free time for energy reduction
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
PowerViP: Soc power estimation framework at transaction level
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
An automated, reconfigurable, low-power RFID tag
Proceedings of the 43rd annual Design Automation Conference
Leakage-aware intraprogram voltage scaling for embedded processors
Proceedings of the 43rd annual Design Automation Conference
The XTREM power and performance simulator for the Intel XScale core: Design and experiences
ACM Transactions on Embedded Computing Systems (TECS)
An automated, FPGA-based reconfigurable, low-power RFID tag
Microprocessors & Microsystems
Joint throughput and energy optimization for pipelined execution of embedded streaming applications
Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Accurate and fast system-level power modeling: An XScale-based case study
ACM Transactions on Embedded Computing Systems (TECS) - Special Section LCTES'05
Radio frequency identification prototyping
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Accurate and fast system-level power modeling: An XScale-based case study
ACM Transactions on Embedded Computing Systems (TECS)
Accurate and scalable simulation of network of heterogeneous sensor devices
Journal of Signal Processing Systems - Special Issue: Embedded computing systems for DSP
Scenario selection and prediction for DVS-aware scheduling of multimedia applications
Journal of Signal Processing Systems - Special Issue: Embedded computing systems for DSP
Instruction cache energy saving through compiler way-placement
Proceedings of the conference on Design, automation and test in Europe
Exploring and predicting the architecture/optimising compiler co-design space
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
Profiling of lossless-compression algorithms for a novel biomedical-implant architecture
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Power-aware scoreboard alternatives for multimedia processors
Microprocessors & Microsystems
An energy-delay efficient 2-level data cache architecture for embedded system
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Journal of Embedded Computing - PATMOS 2007 selected papers on low power electronics
Energy simulation of embedded XScale systems with XEEMU
Journal of Embedded Computing - PATMOS 2007 selected papers on low power electronics
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Compiler-directed dynamic voltage scaling using program phases
HiPC'07 Proceedings of the 14th international conference on High performance computing
Proceedings of the 20th symposium on Great lakes symposium on VLSI
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
TLB index-based tagging for cache energy reduction
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Hardware cost estimation for application-specific processor design
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
ACM Transactions on Embedded Computing Systems (TECS)
Quasi-static fault-tolerant scheduling schemes for energy-efficient hard real-time systems
Journal of Systems and Software
Adopting TLB index-based tagging to data caches for tag energy reduction
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Fast and accurate embedded systems energy characterization using non-intrusive measurements
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
XEEMU: an improved xscale power simulator
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
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Managing power concerns in icroprocessors has become a pressing research problem across the domains of computer architecture, CAD, and compilers. As a result, several parameterized cycle-level power simulators have been introduced. While these simulators can be quite useful for microarchitectural studies, their generality limits how accurate they can be for any one chip family. Furthermore, their hardware focus means that they do not explicitly enable studying the interaction of different software layers, such as Java applications and their underlying Runtime system software.This paper describes and evaluates XTREM, a power simulation tool tailored for the Intel XScale icroarchitecture. In building XTREM, our goals were to develop a icroarchitecture simulator that, while still offering size parameterizations for cache, TLB, etc., more accurately reflected a realistic processor pipeline. We present a detailed set of validations based on ultimeter power measurements and hardware performance counter sampling. Based on these validations across a wide range of stressmarks, Java benchmarks, and non-Java benchmarks, XTREM has an average performance error of only 6.5% and an even smaller average power error: 4%. The paper goes on to present a selection of application studies enabled by the simulator. For example, presenting power behavior vs. time for selected embedded C and Java CLDC benchmarks, we can make power distinctions between the two programming domains as well as distinguishing Java application (JITted code) power from Java Runtime system power. We also study how the Intel XScale core 's power consumption varies for different data activity factors, creating power swings as large as 50mW for a 200Mhz core. We are planning to release XTREM for wider use, and feel that it offers a useful step forward for compiler and embedded software designers.