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ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Data cache energy minimizations through programmable tag size matching to the applications
Proceedings of the 14th international symposium on Systems synthesis
Direct addressed caches for reduced power consumption
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
A history-based I-cache for low-energy multimedia applications
Proceedings of the 2002 international symposium on Low power electronics and design
Energy frugal tags in reprogrammable I-caches for application-specific embedded processors
Proceedings of the tenth international symposium on Hardware/software codesign
Low cost instruction cache designs for tag comparison elimination
Proceedings of the 2003 international symposium on Low power electronics and design
XTREM: a power simulator for the Intel XScale® core
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Microarchitectural techniques for power gating of execution units
Proceedings of the 2004 international symposium on Low power electronics and design
Tag Overflow Buffering: An Energy-Efficient Cache Architecture
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
Dynamic tag reduction for low-power caches in embedded systems with virtual memory
International Journal of Parallel Programming
Compressed tag architecture for low-power embedded cache systems
Journal of Systems Architecture: the EUROMICRO Journal
SimTag: exploiting tag bits similarity to improve the reliability of the data caches
Proceedings of the Conference on Design, Automation and Test in Europe
TLB index-based tagging for cache energy reduction
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
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Conventional cache tag matching is based on addresses to identify requested data. However, this address-based tagging scheme is not efficient because unnecessarily many tag bits are used. Previous studies show that TLB index-based tagging (TLBIT) can be used in caches because there are not many different tags at a moment due to spatial locality, and those tags are conventionally captured by TLBs. In this paper, we show that directly adopting TLBIT is not effective for data caches because TLBIT incurs large overheads in terms of performance and energy consumption due to cache line searches and invalidations. To achieve true potential of TLBIT, we propose three novel techniques: search zone, c-LRU and TLB buffer. Search zone reduces unnecessary cache line searches and c-LRU reduces cache line invalidations. Finally, TLB buffer prevents immediate cache line invalidations on TLB misses. From our experiments, the proposed techniques reduce overall dynamic energy consumption of the data cache by 8.9% on average. Performance impact is small, less than 0.2% on average.