Partial Resolution in Branch Target Buffers
IEEE Transactions on Computers
A low power unified cache architecture providing power and performance flexibility (poster session)
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Data cache energy minimizations through programmable tag size matching to the applications
Proceedings of the 14th international symposium on Systems synthesis
Partial Resolution in Data Value Predictors
ICPP '00 Proceedings of the Proceedings of the 2000 International Conference on Parallel Processing
Partial Tag Comparison: A New Technology for Power-Efficient Set-Associative Cache Designs
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Tag Overflow Buffering: An Energy-Efficient Cache Architecture
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
TLB index-based tagging for cache energy reduction
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Adopting TLB index-based tagging to data caches for tag energy reduction
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
| Hi-index | 0.01 |
Processors in embedded systems mostly employ cache architectures in order to alleviate the access latency gap between processors and memory systems. Caches in embedded systems usually occupy a major fraction of the implemented chip area. The power dissipation of cache system thus constitutes a significant fraction of the power dissipated by the entire processor in embedded systems. In this paper, we propose the compressed tag architecture to reduce the power dissipation of the tag store in cache systems. We introduce a new tag-matching mechanism by using a locality buffer and a tag compression technique. The main power reduction feature of our proposal is the use of small tag space matching instead of full tag matching, with modest additional hardware costs. The simulation results show that the proposed model provides a power and energy-delay product reduction of up to 27.8% and 26.5%, respectively, while still providing a comparable level of system performance to regular cache systems.